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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda1fc09e4sm502265185a.3.2026.03.12.23.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 23:15:37 -0700 (PDT) From: Wenmeng Liu Date: Fri, 13 Mar 2026 14:15:06 +0800 Subject: [PATCH v9 3/3] media: qcom: camss: tpg: Add TPG support for multiple targets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-camss_tpg-v9-3-b9095de6525b@oss.qualcomm.com> References: <20260313-camss_tpg-v9-0-b9095de6525b@oss.qualcomm.com> In-Reply-To: <20260313-camss_tpg-v9-0-b9095de6525b@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773382521; l=18289; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=Uuk3nG9vfMEKVYDbuxvwjKzt4Bppq0hLE03g972naTI=; b=DWmSJW+yhlVEsErfVQpWateK73zTXS2L1MqPASKh/cgwRnAzisDS3guyoR4L9cnZA0xfhGXBh /JQCCk3Y0YFCMn/gkhs5VB+5uA8NvFo34O3tX/3Py3g+LTQoJdiDbDo X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-GUID: 7rHjVjNI4e79BLJOAMpsJ_N6GZHccsBT X-Authority-Analysis: v=2.4 cv=BNG+bVQG c=1 sm=1 tr=0 ts=69b3ab8a cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=2NXLIIr8FHgYEdIXSdsA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: 7rHjVjNI4e79BLJOAMpsJ_N6GZHccsBT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA0OCBTYWx0ZWRfX7iyF5NKjCjM5 CLuE8GxC1qKuekNiBxPGVyOQAu1hwUbakSjxeVmGCfqIu53jYE0soL+MxHumZtXW4ujCqTuxFef M08ehjDXPhCslketsHkTEdRIXr+GlpQCoNm2m+D8+R8Vv5XmGs/kZB1MLAT6u5J4+WIfSFps5p0 WG0bajAqfvCTOt/oEt95R7myYZM/rrxh5p9xn56hi1a4DjhBsArGfpk4IkkKkqZbS6o0frZ+KSV D34Lbn4yIg7sLtp9co/KJC/z51nYg/2JkZ4oAphJg2UFp1+P1DXA7TaS8Ufvc6skT27Axm2Tng4 Q5Rzfhodd9PeE1/6sD1xpvx5YcIBZxbsiLVK0h9gnZZw8QKdjp9/ZXglb646sMc6wib0jwTlAFu SZVg8sBsClh6JGhS7HNP9wJpHzVuL50lOqbvnFDYN9Ta1NT0nIfDtKIxQ+r/8t82Z2aAcemjled V9Uk3x81Tyc7CgZzDzg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_03,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130048 Add support for TPG found on LeMans, Monaco, Hamoa. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-csid-680.c | 14 +- .../media/platform/qcom/camss/camss-csid-gen3.c | 14 +- drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 231 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 117 ++++++++++- 5 files changed, 371 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index d747aa7db3c12ad27d986e0b2b85a44870f89ad3..27898b3cc7d3c8f275567f81f09= 52e2a0e18f189 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -16,6 +16,7 @@ qcom-camss-objs +=3D \ camss-format.o \ camss-ispif.o \ camss-tpg.o \ + camss-tpg-gen1.o \ camss-vfe.o \ camss-vfe-4-1.o \ camss-vfe-4-7.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/m= edia/platform/qcom/camss/camss-csid-680.c index 3ad3a174bcfb8c0d319930d0010df92308cb5ae4..2e4547455d229227ba7cc339a13= 271fb28e103a5 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -103,6 +103,8 @@ #define CSI2_RX_CFG0_PHY_NUM_SEL 20 #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 +#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) +#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) =20 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN BIT(0) @@ -185,10 +187,20 @@ static void __csid_configure_rx(struct csid_device *c= sid, struct csid_phy_config *phy, int vc) { u32 val; + struct camss *camss; =20 + camss =3D csid->camss; val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; + + if (camss->tpg && csid->tpg_linked && + camss->tpg[phy->csiphy_id].testgen.mode !=3D TPG_PAYLOAD_MODE_DISABLE= D) { + val |=3D FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1); + val |=3D CSI2_RX_CFG0_TPG_MUX_EN; + } else { + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + } =20 writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0cac662b02f8b920cd1c72db0aeb2..40d79d94068d1ee1c2dfe1c6a01= f3c692144e473 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -66,6 +66,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) +#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) =20 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -109,10 +111,20 @@ static void __csid_configure_rx(struct csid_device *c= sid, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; =20 + camss =3D csid->camss; val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; + + if (camss->tpg && csid->tpg_linked && + camss->tpg[phy->csiphy_id].testgen.mode !=3D TPG_PAYLOAD_MODE_DISABLE= D) { + val |=3D FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1); + val |=3D CSI2_RX_CFG0_TPG_MUX_EN; + } else { + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + } =20 writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..4cffa5e4d7058d7c895c97a0b4e= 808ace4b0bf79 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG (Test Pattern Generator) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +/* TPG global registers */ +#define TPG_HW_VERSION 0x0 +# define HW_VERSION_STEPPING GENMASK(15, 0) +# define HW_VERSION_REVISION GENMASK(27, 16) +# define HW_VERSION_GENERATION GENMASK(31, 28) + +#define TPG_HW_VER(gen, rev, step) \ + (((u32)(gen) << 28) | ((u32)(rev) << 16) | (u32)(step)) + +#define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0) +#define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0) + +#define TPG_HW_STATUS 0x4 + +#define TPG_CTRL 0x64 +# define TPG_CTRL_TEST_EN BIT(0) +# define TPG_CTRL_PHY_SEL BIT(3) +# define TPG_CTRL_NUM_ACTIVE_LANES GENMASK(5, 4) +# define TPG_CTRL_VC_DT_PATTERN_ID GENMASK(8, 6) +# define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) +# define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) + +#define TPG_CLEAR 0x1F4 + +/* TPG VC-based registers */ +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +# define TPG_VC_n_CFG0_VC_NUM GENMASK(4, 0) +# define TPG_VC_n_CFG0_NUM_ACTIVE_DT GENMASK(9, 8) +# define TPG_VC_n_CFG0_NUM_BATCH GENMASK(15, 12) +# define TPG_VC_n_CFG0_NUM_FRAMES GENMASK(31, 16) + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +# define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN GENMASK(2, 0) +# define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN BIT(3) +# define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN BIT(4) +# define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN BIT(5) +# define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD GENMASK(13, 8) +# define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN BIT(16) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_X GENMASK(26, 24) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y GENMASK(30, 28) + +/* TPG DT-based registers */ +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT GENMASK(15, 0) +# define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_1_DATA_TYPE GENMASK(5, 0) +# define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK GENMASK(13, 8) +# define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE GENMASK(3, 0) +/* v2.0.0: USER[19:4], ENC[23:20] */ +# define TPG_V2_0_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(19, 4) +# define TPG_V2_0_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(23, 20) +/* v2.1.0: USER[27:4], ENC[31:28] */ +# define TPG_V2_1_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(27, 4) +# define TPG_V2_1_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(31, 28) + +#define TPG_HBI_PCT_DEFAULT 545 /* 545% */ +#define TPG_VBI_PCT_DEFAULT 10 /* 10% */ +#define PERCENT_BASE 100 + +/* Default user-specified payload for TPG test generator. + * Keep consistent with CSID TPG default: 0xBE. + */ +#define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE +#define TPG_LFSR_SEED_DEFAULT 0x12345678 +#define TPG_COLOR_BARS_CFG_STANDARD \ + FIELD_PREP(TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD, 0xA) + +static const char * const testgen_payload_modes[] =3D { + [TPG_PAYLOAD_MODE_DISABLED] =3D "Disabled", + [TPG_PAYLOAD_MODE_INCREMENTING] =3D "Incrementing", + [TPG_PAYLOAD_MODE_ALTERNATING_55_AA] =3D "Alternating 0x55/0xAA", + [TPG_PAYLOAD_MODE_RANDOM] =3D "Pseudo-random Data", + [TPG_PAYLOAD_MODE_USER_SPECIFIED] =3D "User Specified", + [TPG_PAYLOAD_MODE_COLOR_BARS] =3D "Color bars", +}; + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg =3D &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 payload_mode =3D (tg->mode > TPG_PAYLOAD_MODE_DISABLED) ? + tg->mode - 1 : 0; + u8 lane_cnt =3D tpg->res->lane_cnt; + u8 vc, dt, last_vc =3D 0; + u32 val; + + for (vc =3D 0; vc <=3D MSM_TPG_ACTIVE_VC; vc++) { + last_vc =3D vc; + + input_format =3D &tpg->fmt; + format =3D tpg_get_fmt_entry(tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + if (IS_ERR(format)) + return -EINVAL; + + /* VC configuration */ + val =3D FIELD_PREP(TPG_VC_n_CFG0_NUM_ACTIVE_DT, MSM_TPG_ACTIVE_DT) | + FIELD_PREP(TPG_VC_n_CFG0_NUM_FRAMES, 0); + writel(val, tpg->base + TPG_VC_n_CFG0(vc)); + + writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(vc)); + + val =3D DIV_ROUND_UP(input_format->width * format->bpp * TPG_HBI_PCT_DEF= AULT, + BITS_PER_BYTE * lane_cnt * PERCENT_BASE); + writel(val, tpg->base + TPG_VC_n_HBI_CFG(vc)); + + val =3D input_format->height * TPG_VBI_PCT_DEFAULT / PERCENT_BASE; + writel(val, tpg->base + TPG_VC_n_VBI_CFG(vc)); + + writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(= vc)); + + /* DT configuration */ + for (dt =3D 0; dt <=3D MSM_TPG_ACTIVE_DT; dt++) { + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT, + input_format->height & 0xffff) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH, + input_format->width & 0xffff); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(vc, dt)); + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_1_DATA_TYPE, format->data_type); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(vc, dt)); + + if (tpg->hw_version =3D=3D TPG_HW_VER_2_0_0) { + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, payload_mode) | + FIELD_PREP(TPG_V2_0_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_V2_0_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT, + format->encode_format); + } else if (tpg->hw_version >=3D TPG_HW_VER_2_1_0) { + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, payload_mode) | + FIELD_PREP(TPG_V2_1_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_V2_1_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT, + format->encode_format); + } + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(vc, dt)); + } + } + + /* Global TPG control */ + val =3D FIELD_PREP(TPG_CTRL_TEST_EN, 1) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc); + writel(val, tpg->base + TPG_CTRL); + + return 0; +} + +static int tpg_reset(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + tpg_reset(tpg); +} + +static int tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + if (enable) + return tpg_stream_on(tpg); + + tpg_stream_off(tpg); + + return 0; +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val >=3D 0 && val <=3D TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode =3D val; + + return 0; +} + +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version =3D readl(tpg->base + TPG_HW_VERSION); + + tpg->hw_version =3D hw_version; + dev_dbg(tpg->camss->dev, "tpg HW Version =3D %u.%u.%u\n", + (u32)FIELD_GET(HW_VERSION_GENERATION, hw_version), + (u32)FIELD_GET(HW_VERSION_REVISION, hw_version), + (u32)FIELD_GET(HW_VERSION_STEPPING, hw_version)); + + return hw_version; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes =3D testgen_payload_modes; + tpg->testgen.nmodes =3D TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 =3D { + .configure_stream =3D tpg_configure_stream, + .configure_testgen_pattern =3D tpg_configure_testgen_pattern, + .hw_version =3D tpg_hw_version, + .reset =3D tpg_reset, + .subdev_init =3D tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 1de35bcd8e5fc6eaa9dab537960520b2c07dd830..bb4efeae55ceea2a6e0109b64de= cd3be11dd26d5 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3559,6 +3559,54 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, }; =20 +static const struct camss_subdev_resources tpg_res_8775p[] =3D { + /* TPG0 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "csiphy_rx" }, + .clock_rate =3D { + { 0 }, + { 400000000 }, + }, + .reg =3D { "tpg0" }, + .tpg =3D { + .lane_cnt =3D 4, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + /* TPG1 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "csiphy_rx" }, + .clock_rate =3D { + { 0 }, + { 400000000 }, + }, + .reg =3D { "tpg1" }, + .tpg =3D { + .lane_cnt =3D 4, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + /* TPG2 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "csiphy_rx" }, + .clock_rate =3D { + { 0 }, + { 400000000 }, + }, + .reg =3D { "tpg2" }, + .tpg =3D { + .lane_cnt =3D 4, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] =3D { /* CSID0 */ { @@ -3963,6 +4011,54 @@ static const struct camss_subdev_resources csiphy_re= s_x1e80100[] =3D { }, }; =20 +static const struct camss_subdev_resources tpg_res_x1e80100[] =3D { + /* TPG0 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "csid_csiphy_rx" }, + .clock_rate =3D { + { 0 }, + { 400000000 }, + }, + .reg =3D { "csitpg0" }, + .tpg =3D { + .lane_cnt =3D 4, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + /* TPG1 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "csid_csiphy_rx" }, + .clock_rate =3D { + { 0 }, + { 400000000 }, + }, + .reg =3D { "csitpg1" }, + .tpg =3D { + .lane_cnt =3D 4, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + /* TPG2 */ + { + .regulators =3D {}, + .clock =3D { "cpas_ahb", "csid_csiphy_rx" }, + .clock_rate =3D { + { 0 }, + { 400000000 }, + }, + .reg =3D { "csitpg2" }, + .tpg =3D { + .lane_cnt =3D 4, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_x1e80100[] =3D { /* CSID0 */ { @@ -4076,7 +4172,7 @@ static const struct camss_subdev_resources vfe_res_x1= e80100[] =3D { .clock =3D {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb", "vfe0" }, - .clock_rate =3D { { 0 }, + .clock_rate =3D { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -4100,7 +4196,7 @@ static const struct camss_subdev_resources vfe_res_x1= e80100[] =3D { .clock =3D { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "cpas_fast_ahb", "cpas_vfe1", "vfe1_fast_ahb", "vfe1" }, - .clock_rate =3D { { 0 }, + .clock_rate =3D { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -4124,7 +4220,7 @@ static const struct camss_subdev_resources vfe_res_x1= e80100[] =3D { .clock =3D { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", "vfe_lite_csid" }, - .clock_rate =3D { { 0 }, + .clock_rate =3D { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -4147,7 +4243,7 @@ static const struct camss_subdev_resources vfe_res_x1= e80100[] =3D { .clock =3D { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", "vfe_lite_csid" }, - .clock_rate =3D { { 0 }, + .clock_rate =3D { { 400000000 }, { 0 }, { 0 }, { 0 }, @@ -5030,6 +5126,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; =20 + if (camss->res->tpg_num > 0) { + camss->tpg =3D devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid =3D devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->cs= id), GFP_KERNEL); if (!camss->csid) @@ -5219,11 +5322,13 @@ static const struct camss_resources qcs8300_resourc= es =3D { .version =3D CAMSS_8300, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8300, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_qcs8300, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8300), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_qcs8300), @@ -5233,11 +5338,13 @@ static const struct camss_resources sa8775p_resourc= es =3D { .version =3D CAMSS_8775P, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8775p, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_sa8775p, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8775p), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_sa8775p), @@ -5360,12 +5467,14 @@ static const struct camss_resources x1e80100_resour= ces =3D { .version =3D CAMSS_X1E80100, .pd_name =3D "top", .csiphy_res =3D csiphy_res_x1e80100, + .tpg_res =3D tpg_res_x1e80100, .csid_res =3D csid_res_x1e80100, .vfe_res =3D vfe_res_x1e80100, .csid_wrapper_res =3D &csid_wrapper_res_x1e80100, .icc_res =3D icc_res_x1e80100, .icc_path_num =3D ARRAY_SIZE(icc_res_x1e80100), .csiphy_num =3D ARRAY_SIZE(csiphy_res_x1e80100), + .tpg_num =3D ARRAY_SIZE(tpg_res_x1e80100), .csid_num =3D ARRAY_SIZE(csid_res_x1e80100), .vfe_num =3D ARRAY_SIZE(vfe_res_x1e80100), }; --=20 2.34.1