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Fri, 13 Mar 2026 06:39:32 +0000 (GMT) Received: from NP-G-BRAJESH.pu.imgtec.org (172.25.128.99) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 13 Mar 2026 06:39:29 +0000 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:24 +0000 Subject: [PATCH v2 1/2] drm/imagination: Improve firmware power off for layout_mars config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260313-b4-staging-layout_mars_base-v2-1-9e3c251d278e@imgtec.com> References: <20260313-b4-staging-layout_mars_base-v2-0-9e3c251d278e@imgtec.com> In-Reply-To: <20260313-b4-staging-layout_mars_base-v2-0-9e3c251d278e@imgtec.com> To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Alessio Belle , Alexandru Dadu CC: , , "Brajesh Gupta" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Skip checks for those from kernel and check idle bits for Firmware MCU and system arbiter excluding SOCIF. Signed-off-by: Brajesh Gupta --- drivers/gpu/drm/imagination/pvr_fw_startstop.c | 85 +++++++++++++++++-----= ---- 1 file changed, 57 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/d= rm/imagination/pvr_fw_startstop.c index dcbb9903e791..e47224ac0547 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c @@ -209,18 +209,32 @@ pvr_fw_stop(struct pvr_device *pvr_dev) ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN | ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN); bool skip_garten_idle =3D false; + u64 layout_mars_value =3D 0; + bool layout_mars =3D false; + bool meta_fw =3D pvr_dev->fw_dev.processor_type =3D=3D PVR_FW_PROCESSOR_T= YPE_META; u32 reg_value; int err; =20 + if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) =3D=3D 0) + layout_mars =3D layout_mars_value > 0; + /* - * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. - * For cores with the LAYOUT_MARS feature, SIDEKICK would have been + * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have be= en * powered down by the FW. */ - err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_= mask, - sidekick_idle_mask, POLL_TIMEOUT_USEC); - if (err) - return err; + if (!layout_mars) { + /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.= */ + err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle= _mask, + sidekick_idle_mask, POLL_TIMEOUT_USEC); + if (err) + return err; + + /* Wait for SLC to signal IDLE. */ + err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ROGUE_CR_SLC_IDLE_= MASKFULL, + ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); + if (err) + return err; + } =20 /* Unset MTS DM association with threads. */ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC, @@ -270,27 +284,25 @@ pvr_fw_stop(struct pvr_device *pvr_dev) return err; =20 /* - * Wait for SLC to signal IDLE. - * For cores with the LAYOUT_MARS feature, SLC would have been powered - * down by the FW. + * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have be= en + * powered down by the FW. */ - err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, - ROGUE_CR_SLC_IDLE_MASKFULL, - ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); - if (err) - return err; + if (!layout_mars) { + /* Wait for SLC to signal IDLE. */ + err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, + ROGUE_CR_SLC_IDLE_MASKFULL, + ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); + if (err) + return err; =20 - /* - * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. - * For cores with the LAYOUT_MARS feature, SIDEKICK would have been power= ed - * down by the FW. - */ - err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_= mask, - sidekick_idle_mask, POLL_TIMEOUT_USEC); - if (err) - return err; + /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.= */ + err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle= _mask, + sidekick_idle_mask, POLL_TIMEOUT_USEC); + if (err) + return err; + } =20 - if (pvr_dev->fw_dev.processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_META) { + if (meta_fw) { err =3D pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value); if (err) return err; @@ -304,11 +316,28 @@ pvr_fw_stop(struct pvr_device *pvr_dev) skip_garten_idle =3D true; } =20 - if (!skip_garten_idle) { - err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, - ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, - ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, + if (meta_fw || !layout_mars) { + if (!skip_garten_idle) { + err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, + ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, + ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, + POLL_TIMEOUT_USEC); + if (err) + return err; + } + } else { + /* + * As FW core has been moved from SIDEKICK to the new MARS domain, check= ing + * idle bits for CPU & System Arbiter excluding SOCIF which will never be + * idle if Host polling on this register + */ + err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE, + ROGUE_CR_MARS_IDLE_CPU_EN | + ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, + ROGUE_CR_MARS_IDLE_CPU_EN | + ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, POLL_TIMEOUT_USEC); + if (err) return err; } --=20 2.43.0 From nobody Tue Apr 7 13:09:45 2026 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAC9E316199 for ; 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Signed-off-by: Brajesh Gupta --- drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/d= rm/imagination/pvr_fw_startstop.c index e47224ac0547..2f90bc1bf084 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c @@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev) pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, - ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, - ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + + if (meta_fw) { + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, + ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, + ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + } =20 /* Extra Idle checks. */ err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, --=20 2.43.0