From nobody Tue Apr 7 13:10:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75A4738423D; Fri, 13 Mar 2026 10:07:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773396461; cv=none; b=e9P9Kcj3v1ay/2HIb1mImD2L1XwsHITFXHjtDvehiK/8CqZqgwYDbxYqlY8bgbEvGXunH0z/WD0ok3T6iSzkpYAbDU0v0gSS+QApXyWzo7cSr6T/OCNo57LnpSbFfaqarI+SHL5BnNvRoGmGEwWfCCTBHy6h81qiS9475EBogpI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773396461; c=relaxed/simple; bh=GI5A6sIDTkRHuW8a/SgtskqxywWH7KKoxYkTh0qrVok=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EYc7PLb7ZL+Sm3U3UcJVnGlS0iM+Dql1u2i1HBbUzyofiX4c2AZXEGidV2ri3bG72M1Ny+6/diJ3Dmi00tn8B6xmzQfPRVlAYiT5IoHZsvG3E5OnMsNLDJY/Tp09koGzb+7FgiR5rzHWvpPey6XUYXqpf/KGEe7ADZYdd8a5m8w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bzrSWSIc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bzrSWSIc" Received: by smtp.kernel.org (Postfix) with ESMTPS id 317D7C19421; Fri, 13 Mar 2026 10:07:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773396461; bh=GI5A6sIDTkRHuW8a/SgtskqxywWH7KKoxYkTh0qrVok=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bzrSWSIc1ENoTTXhwORkNWxyNxkOqohR4gqsYT8NQp4IZkSKuHfe1UNZVxulSX8qY 4upITLZWOPsH9+FT0edMmgiNWChTcxDT0C1Eeq1StBsBSJTunbtD9aPPS0iSNhrIiN znIBauMP8c6uB+rHsPVKvG8XMUrZfrbyOyI/b1tAAjDHDdaamt4XnGxbbvmN6G2XgR +4257sLCcr93KcahbGxJPJWnYpbL2fp7/w8K/VvgKK/yKTpQfwaD02Qdxl6B2z3UPu mB5TwewSPhmbmofYZRScvXkKXQqnJuy7pGQF6cmxtMC2DrCzmCndGWNZ056a2p+UiL 1Ntq8hNoe/H+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 206DA105F78B; Fri, 13 Mar 2026 10:07:41 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Fri, 13 Mar 2026 12:07:25 +0200 Subject: [PATCH v3 1/4] dt-bindings: iio: adc: add bindings for AD4691 family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-ad4692-multichannel-sar-adc-driver-v3-1-b4d14d81a181@analog.com> References: <20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com> In-Reply-To: <20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773396456; l=7296; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=oJ+skzTO+ldVyCAp6LzsSaIW3BVvqyXV5zmKWF0Z/GQ=; b=U9uUEwwFsZs5v0+at5LAoz4KhSbzNVWFTLPt5bpOeFmpVRerc9avumDdrNlGW13zGWDzir0a4 xTzVsTGq4AMDvYrBGE2c6f4X9f0JURjRmOo5Ql0sIEBlT9/ILAGnMDx X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add DT bindings for the Analog Devices AD4691 family of multichannel SAR ADCs (AD4691, AD4692, AD4693, AD4694). The binding describes the hardware connections: an optional PWM on the CNV pin selects CNV Clock Mode; when absent, Manual Mode is used with CNV tied to SPI CS. GPIO pins, voltage supplies, and the trigger-source interface for SPI Engine offload operation are also described. Signed-off-by: Radu Sabau --- .../devicetree/bindings/iio/adc/adi,ad4691.yaml | 180 +++++++++++++++++= ++++ MAINTAINERS | 8 + include/dt-bindings/iio/adc/adi,ad4691.h | 13 ++ 3 files changed, 201 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4691.yaml new file mode 100644 index 000000000000..a9301e0ca851 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4691 Family Multichannel SAR ADCs + +maintainers: + - Radu Sabau + +description: | + The AD4691 family are high-speed, low-power, multichannel successive + approximation register (SAR) analog-to-digital converters (ADCs) with + an SPI-compatible serial interface. The ADC supports CNV Clock Mode, + where an external PWM drives the CNV pin, and Manual Mode, where CNV + is directly tied to the SPI chip-select. + + Datasheets: + * https://www.analog.com/en/products/ad4692.html + * https://www.analog.com/en/products/ad4691.html + * https://www.analog.com/en/products/ad4694.html + * https://www.analog.com/en/products/ad4693.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4691 + - adi,ad4692 + - adi,ad4693 + - adi,ad4694 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + spi-cpol: true + spi-cpha: true + + vio-supply: + description: I/O voltage supply (1.71V to 1.89V or VDD). + + vref-supply: + description: External reference voltage supply (2.4V to 5.25V). + + vrefin-supply: + description: Internal reference buffer input supply. + + reset-gpios: + description: GPIO connected to the RESET pin (active high). + maxItems: 1 + + clocks: + description: Reference clock for PWM timing in CNV Clock Mode. + maxItems: 1 + + pwms: + description: + PWM connected to the CNV pin. When present, selects CNV Clock Mode w= here + the PWM drives the conversion rate. When absent, Manual Mode is used + (CNV tied to SPI CS). + maxItems: 1 + + pwm-names: + items: + - const: cnv + + interrupts: + description: + Interrupt line connected to the ADC GP0 pin. GP0 must be physically + wired to an interrupt-capable input on the SoC. The ADC asserts GP0 = as + DATA_READY at end of conversion, used both for non-offload CNV Clock= Mode + operation and for SPI Engine offload triggering via '#trigger-source= -cells'. + Not used in Manual Mode, where CNV is tied to SPI CS and no DATA_REA= DY + signal is generated. + maxItems: 1 + + '#trigger-source-cells': + description: | + For SPI Engine offload operation, this node acts as a trigger source. + Two cells are required: + - First cell: Trigger event type (0 =3D BUSY, 1 =3D DATA_READY) + - Second cell: GPIO pin number (only 0 =3D GP0 is supported) + + Macros are available in dt-bindings/iio/adc/adi,ad4691.h: + AD4691_TRIGGER_EVENT_BUSY, AD4691_TRIGGER_EVENT_DATA_READY + AD4691_TRIGGER_PIN_GP0 + const: 2 + +required: + - compatible + - reg + - vio-supply + - reset-gpios + +allOf: + # vref-supply and vrefin-supply are mutually exclusive, one is required + - oneOf: + - required: + - vref-supply + - required: + - vrefin-supply + + # CNV Clock Mode requires a reference clock. + - if: + required: + - pwms + then: + required: + - clocks + + # CNV Clock Mode (pwms present) without SPI offload requires a DRDY inte= rrupt. + # Offload configurations expose '#trigger-source-cells' instead. + - if: + required: + - pwms + not: + required: + - '#trigger-source-cells' + then: + required: + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + /* Example: AD4692 in CNV Clock Mode (pwms present) with standard SPI = */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <40000000>; + + vio-supply =3D <&vio_supply>; + vref-supply =3D <&vref_5v>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + + clocks =3D <&ref_clk>; + + pwms =3D <&pwm_gen 0 0>; + pwm-names =3D "cnv"; + + interrupts =3D <12 4>; + }; + }; + + - | + #include + + /* Example: AD4692 in Manual Mode (no pwms) with SPI Engine offload */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <31250000>; + + vio-supply =3D <&vio_supply>; + vrefin-supply =3D <&vrefin_supply>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 61bf550fd37c..9994d107d88d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1484,6 +1484,14 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml F: drivers/iio/adc/ad4170-4.c =20 +ANALOG DEVICES INC AD4691 DRIVER +M: Radu Sabau +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml +F: include/dt-bindings/iio/adc/adi,ad4691.h + ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich M: Nuno S=C3=A1 diff --git a/include/dt-bindings/iio/adc/adi,ad4691.h b/include/dt-bindings= /iio/adc/adi,ad4691.h new file mode 100644 index 000000000000..294b03974f48 --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad4691.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD4691_H +#define _DT_BINDINGS_ADI_AD4691_H + +/* Trigger event types */ +#define AD4691_TRIGGER_EVENT_BUSY 0 +#define AD4691_TRIGGER_EVENT_DATA_READY 1 + +/* Trigger GPIO pin selection */ +#define AD4691_TRIGGER_PIN_GP0 0 + +#endif /* _DT_BINDINGS_ADI_AD4691_H */ --=20 2.43.0