From nobody Thu Apr 2 01:46:33 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8D231A053 for ; Thu, 12 Mar 2026 21:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773351040; cv=none; b=B+Kp/Kp0vtIZIkQihAvwkrNobl4aAsS13sszqxnISqo1YyLimmTN7ZtErnH7+BLFzxEBr9yZc2b1IYAla7yAPbubVsGLD+vsG/GJYWObRXOS6BLNUZWu6LMxP4enpJSgNYj/zd2+QyrdgjO88SSMiQ9xAFQ4uofgZUGOL7OO7FM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773351040; c=relaxed/simple; bh=XgLi6lZ5iOzM1+Q8PrRh4//Lz5Qucdxy8UtxaXm1w5Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BNfX4w5Jgw4AkpvWPAa4poyA/684MsEN6dSfyv08g9PtupGG6S8pK79MBSn2VD5nWco5otuwlORuPqF7t7FrLquwLCMBS6nztTieLbrn5VIsJcDEnX56fpEsYeoT8/3VjDREGviSLPvtTEiq0I8+ktcCPQTDn3LZcaoyhzgop1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=sde9qGNd; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="sde9qGNd" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=+ndxK5vZOqleTR6mNTO46jmD+gZjjkUpfKpUFMPP7ZI=; b=sde9qGNdMZMGE4/E7Q2HX8XM2w 2kyhOVVFHPKG4nazzdezNhm3V8LllGSAw1ZVjO2mpomse8nuMH6sL4RJflp8g/luEVjJJkU0JI+hX N0Iln/DpezslarLqMM8ibwZHRorDgkc2e0bm1uoacYsLxENAZIbUz0U56zrXxvL9Ed4CFROOcEQGX 4q5Noo12aZvdzpxfeLtMdbyAZNHZiSgqpfv8Xn/cKfw28X1Y6Hj8CFTsCtLHI8jgIkNKv0j/Kac4h mNKvO+I5ieqp/t6ZAawF1EZs7SiLN1N+G/XmEUkTpK3KyijtDrKFatbnfmGtF+8Mvm3fWwlQAc89E s9T1S3+A==; From: Heiko Stuebner To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, finley.xiao@rock-chips.com, w@1wt.eu, jonas@kwiboo.se Subject: [PATCH v2 3/3] arm64: dts: rockchip: Enable OTP controller for RK3528 Date: Thu, 12 Mar 2026 22:30:19 +0100 Message-ID: <20260312213019.13965-4-heiko@sntech.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260312213019.13965-1-heiko@sntech.de> References: <20260312213019.13965-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonas Karlman Enable the One Time Programmable Controller (OTPC) in RK3528 and add an initial nvmem fixed layout. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index d402f2828814..806b8109f67d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1190,6 +1190,53 @@ sdmmc: mmc@ffc30000 { status =3D "disabled"; }; =20 + otp: efuse@ffce0000 { + compatible =3D "rockchip,rk3528-otp"; + reg =3D <0x0 0xffce0000 0x0 0x4000>; + clocks =3D <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_SBPI_OTPC_NS>; + clock-names =3D "otp", "apb_pclk", "sbpi"; + resets =3D <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_SBPI_OTPC_NS>; + reset-names =3D "otp", "apb", "sbpi"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + logic_leakage: logic-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + gpu_leakage: gpu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + + tsadc_trim: tsadc-trim@44 { + reg =3D <0x44 0x2>; + bits =3D <0 10>; + }; + }; + }; + dmac: dma-controller@ffd60000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x0 0xffd60000 0x0 0x4000>; --=20 2.47.3