From nobody Thu Apr 2 01:53:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAA17383C8C for ; Thu, 12 Mar 2026 21:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773351039; cv=none; b=M75FZAqodqHbxLFH+/601J0gVMhZQlFf92gCnfBhiH03mR4SBoLX/r2k6/WX8OCuwIhH12jgarE9IEPAZgFa8hPj6/BcUuhbczrDJtKiwtlsBev24+dUpSOb7glmHr5eln1vla2T4ZdlIn+2Qcos4Jj+S08Kd6xfMFH1qftu29U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773351039; c=relaxed/simple; bh=hQnoZTjtLgbZlhiqAwg8tr+8cuW042zxyFhxtFeqlg4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f109nJw4VHybXsn7wS4/w6BpRb/WfFJwg5k0RJqUCd7yJbgWpIUq6iByvg6KACv9AdpgDvFGMUPRp5EaFDGcvRbinWcuuN59VSDPeUs2oKJRc4WAaEbXTnARP1il0TGBglxf6oUjTduU/ArWQPFs0I2e3d/1viYYYwnqkXs6iyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=rB78n+Km; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="rB78n+Km" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=h4MC6TZxbYtbW++aJnjTwi5qHIz2Y5mW4BPCtPUKHPk=; b=rB78n+KmyKiiQVYIuyT+Zej62M C0aBAQPFEDGM2qLUyw/1gMLFAxhaQAzg9f5hvYMCku5pMrHd8HZyh95EKNROKJsJe1J4mBpL5aXAj bH2DCry+M3kN2vWhwxmD5pp3z812UnCoUx1xAvWp+m0Kde1un8r59VV7pmzFVJXt05AeMCaEkDfYI /mfnQ0NsEpvUGzQI6tmyoeyeEZw2gwTAJ8Uz0C8qyEk7BKsAoTN36rjAjrKFCzmZybDSG6aJZCLVb d+CVQT013rH7XTSIGaq7L7RQutGOIXjRVlZZ1+j732WLai0k7HOQuBnwTuKMDOBPWcDkM3vWIdcyM TP/oZj2Q==; From: Heiko Stuebner To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, finley.xiao@rock-chips.com, w@1wt.eu, jonas@kwiboo.se Subject: [PATCH v2 1/3] arm64: dts: rockchip: Enable OTP controller for RK3562 Date: Thu, 12 Mar 2026 22:30:17 +0100 Message-ID: <20260312213019.13965-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260312213019.13965-1-heiko@sntech.de> References: <20260312213019.13965-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the One Time Programmable Controller (OTPC) in RK3562 and add an initial nvmem fixed layout. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts= /rockchip/rk3562.dtsi index f84676b47b27..e4816aa3dae0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1093,6 +1093,52 @@ sdmmc1: mmc@ff890000 { status =3D "disabled"; }; =20 + otp: efuse@ff930000 { + compatible =3D "rockchip,rk3562-otp"; + reg =3D <0x0 0xff930000 0x0 0x4000>; + clocks =3D <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_SBPI_OTPC_NS>; + clock-names =3D "otp", "apb_pclk", "phy", "sbpi"; + resets =3D <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_P_OTPPHY>, <&cru SRST_SBPI_OTPC_NS>; + reset-names =3D "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg =3D <0x1d 0x1>; + }; + }; + }; + dmac: dma-controller@ff990000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x0 0xff990000 0x0 0x4000>; --=20 2.47.3