From nobody Tue Apr 7 14:38:10 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 923B439098E; Thu, 12 Mar 2026 16:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773334426; cv=none; b=J4axCJYRtCcLLXN4hAJV+mf1cOxpJS4xh53HHdhq6ayLZKa/6cBznlYlb0ABz+D0acgd7pUhwDyAkpTomqrIOaDa/sFWaocsVVMpBFsrZuHbQJatxuuexVu5dF3jpR2o6qLpkjGK/CZcu9EPBqVjEU4SpohyYMu7q0c7s/tb8ZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773334426; c=relaxed/simple; bh=LyKCNssqnl2vztrQOWET61HDjDykU8dsBFmzjj852FQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dlLVBk34sZJGybW4Xb528iLiIsPMDkvQQHU0QrttL6UQp/1mNfhtONnJwIVGssuoS8mZ5f1a/hkx3aVp1xM1JgE8jLQ9T6+Yf/yMTvZSQpMk8l+onuI/KtDI72ZyhJFppnjaIWa9TFhTToq/aF2vhvFqfTqfb30O4djvXHkNwyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=bCBQVD9c; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="bCBQVD9c" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id AEC552C7C38; Thu, 12 Mar 2026 17:53:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773334423; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=XfeLkzD3jHviFHfsrPQFth60rKx2osGAGkwc8bgjjGk=; b=bCBQVD9cJe9/f7Ts4lwAfzQ3rCqUU5OICxzvkbKnmPRDnRBybPrjcJA/h7urTkxBHCtxJy k09A2nov3B6wYJ6EN8nKttBYyUBWdNLK1Gri0xB63RmPl1IqKmc6EJEmOUDVMjabV5VbAa 9XyFkoD77ySp7Id2ZC2dvj/jRm3PUyf++s+ZnYYHN6JuuTcM8YCYJ3NshUJ7W5M5Wbgjrd ZK/1WrPlmszCT2Q+6Q6kJkLiudYWWnBrn4oxy8fTW/ylr0DXunrD6x/0afrVYkCkAXUw+H cglfV/kl2ZFxMJVEeRQpofYKIugKXYxkZhuO99fJfyKarDGQKnbGP8kbYPHL2Q== From: Caleb James DeLisle To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, ryder.lee@mediatek.com, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ansuelsmth@gmail.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle Subject: [PATCH 1/3] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528 Date: Thu, 12 Mar 2026 16:53:30 +0000 Message-Id: <20260312165332.569772-2-cjd@cjdns.fr> In-Reply-To: <20260312165332.569772-1-cjd@cjdns.fr> References: <20260312165332.569772-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Introduce EcoNet EN7528 SoC compatible in MediaTek PCIe controller binding. EcoNet PCIe controller has the same configuration model as Mediatek v2 but is initiallized more similarly to an MT7621 PCIe. Signed-off-by: Caleb James DeLisle --- .../bindings/pci/mediatek-pcie.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index 0b8c78ec4f91..ae95b635f304 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - airoha,an7583-pcie + - econet,en7528-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -226,6 +227,31 @@ allOf: =20 mediatek,pbus-csr: false =20 + - if: + properties: + compatible: + contains: + const: econet,en7528-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + reset: false + + reset-names: false + + power-domain: false + + mediatek,pbus-csr: false + + required: + - phys + - phy-names + unevaluatedProperties: false =20 examples: @@ -436,3 +462,58 @@ examples: }; }; }; + + # EN7528 + - | + #include + #include + #include + + soc_3 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + pcie@1fb81000 { + compatible =3D "econet,en7528-pcie"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x1fb81000 0x1000>; + reg-names =3D "port0"; + + clocks =3D <&scuclk EN7523_CLK_PCIE>; + clock-names =3D "sys_ck0"; + + phys =3D <&pcie_phy0>; + phy-names =3D "pcie-phy0"; + + ranges =3D <0x01000000 0 0x00000000 0x1f600000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x08000000>; + + interrupt-parent =3D <&intc>; + interrupts =3D <23>; + interrupt-names =3D "pcie_irq"; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + slot0: pcie@0,0 { + reg =3D <0x0000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + }; --=20 2.39.5 From nobody Tue Apr 7 14:38:10 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 021FF3FB057; Thu, 12 Mar 2026 16:53:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773334429; cv=none; b=ffAUtx/IP1CoNc6NkZ2Yy4LbBQqvoK1UcS5gwQvqiwxUWOPOAQY4pGAP5o0P5LFvNDqiavDyTzNXFNfjGExNoXQvAir/GUXQ477g0jsADvlT895+TO36P9OFekSDG/WMqDuAU2DEiION+1HIIQfaFDww1zC+pbV0lZu0S7QycfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773334429; c=relaxed/simple; bh=ysFR1jzj0HcTEVWvdyEWNz2bgQMSUEQSobGu9jH/fGs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NW3I/ml7vPQ/NjIRtrO97QKpX82EbFQu6S9jyOnKti0qfjDWKhOtfX43plPsAobB7FKQN41caGsMQCCwHXP5e2WB+9QPc8a86mRFBS/Ic9MdMt0BZTkDqd+mriywuiWr2i3jq5pjoE3I4B6W6lniRUF4E4cAZkILzgR5mEQcmOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=fsNWYQq6; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="fsNWYQq6" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D26A42C7647; Thu, 12 Mar 2026 17:53:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773334425; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=2wRrh0jjOE1IlR0y3h0y6zJysK8/ZS3R6V1I2f9MRJ0=; b=fsNWYQq6USMpXF0rR0mv+U64jAph+cKLF0yfrSDuf0EO7gDAO/vv1mWn4Mb1qF/GvQPzPD M21VhGyb6Nee3jLkiwnjMkqbqymrOPU2kjPl4uf3AsyLU7WOJSvxpHNqzbjjr+Lq32u94N JNcG/W0kcICuYUr1K4XGzjIm1o597SfDThe9mUHuHidbf3d3AeMmmAKHvKNxa8DOxZfD8g sMzZ7D2KsbZ9iitpqRdb0oWiLcx0O1gWDlG2LQySJdE/95MP6DdroTjl/CvzI0DcCtieZU 4eCXnAyQqJeje39IKuo5Uztq85XuC0uugtDRRIvAuLMeCN8CqiI7TRCGQjqVTA== From: Caleb James DeLisle To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, ryder.lee@mediatek.com, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ansuelsmth@gmail.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle Subject: [PATCH 2/3] PCI: mediatek: Add support for EcoNet EN7528 SoC Date: Thu, 12 Mar 2026 16:53:31 +0000 Message-Id: <20260312165332.569772-3-cjd@cjdns.fr> In-Reply-To: <20260312165332.569772-1-cjd@cjdns.fr> References: <20260312165332.569772-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs. These SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports require re-training after startup. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef Co-developed-by: Caleb James DeLisle Signed-off-by: Caleb James DeLisle --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek.c | 118 +++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5aaed8ac6e44..f6a5fcacb38d 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -209,7 +209,7 @@ config PCI_MVEBU =20 config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST depends on OF depends on PCI_MSI select IRQ_MSI_LIB diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 5defa5cc4c2b..84064061652a 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,7 @@ =20 #define PCIE_CONF_VEND_ID 0x100 #define PCIE_CONF_DEVICE_ID 0x102 +#define PCIE_CONF_REV_CLASS 0x104 #define PCIE_CONF_CLASS_ID 0x106 =20 #define PCIE_INT_MASK 0x420 @@ -89,6 +91,11 @@ #define MSI_MASK BIT(23) #define MTK_MSI_IRQS_NUM 32 =20 +#define EN7528_HOST_MODE 0x00804201 +#define EN7528_LINKUP_REG 0x50 +#define EN7528_RC0_LINKUP BIT(1) +#define EN7528_RC1_LINKUP BIT(2) + #define PCIE_AHB_TRANS_BASE0_L 0x438 #define PCIE_AHB_TRANS_BASE0_H 0x43c #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) @@ -753,6 +760,86 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_po= rt *port) return 0; } =20 +static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); + struct resource *mem =3D NULL; + struct resource_entry *entry; + u32 val, link_mask; + int err; + + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (entry) + mem =3D entry->res; + if (!mem) + return -EINVAL; + + if (!pcie->cfg) { + dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n"); + return -EINVAL; + } + + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# + * should be delayed 100ms (TPVPERL) for the power and clock to become + * stable. + */ + msleep(100); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, + port->base + PCIE_CONF_REV_CLASS); + writel(EN7528_HOST_MODE, port->base); + + link_mask =3D (port->slot =3D=3D 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINK= UP; + + /* 100ms timeout value should be enough for Gen1/2 training */ + err =3D regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val, + !!(val & link_mask), 20, + 100 * USEC_PER_MSEC); + if (err) { + dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot); + return -ETIMEDOUT; + } + + /* Set INTx mask */ + val =3D readl(port->base + PCIE_INT_MASK); + val &=3D ~INTX_MASK; + writel(val, port->base + PCIE_INT_MASK); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + mtk_pcie_enable_msi(port); + + /* Set AHB to PCIe translation windows */ + val =3D lower_32_bits(mem->start) | + AHB2PCIE_SIZE(fls(resource_size(mem))); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); + + val =3D upper_32_bits(mem->start); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); + + writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0); + + return 0; +} + static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { @@ -1149,6 +1236,30 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) goto put_resources; =20 + /* Retrain Gen1 links to reach Gen2 where supported */ + if (pcie->soc->startup =3D=3D mtk_pcie_startup_port_en7528) { + struct pci_bus *bus =3D host->bus; + struct pci_dev *rc =3D NULL; + + while ((rc =3D pci_get_class(PCI_CLASS_BRIDGE_PCI << 8, rc))) { + int ret =3D -EOPNOTSUPP; + + if (rc->bus !=3D bus) + continue; + + #if IS_BUILTIN(CONFIG_PCIE_MEDIATEK) + ret =3D pcie_retrain_link(rc, true); + #endif + + if (!ret) + dev_info(dev, "port%d link retrained\n", + PCI_SLOT(rc->devfn)); + else + dev_info(dev, "port%d failed to retrain %pe\n", + PCI_SLOT(rc->devfn), ERR_PTR(ret)); + } + } + return 0; =20 put_resources: @@ -1264,8 +1375,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629= =3D { .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_en7528 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_en7528, + .setup_irq =3D mtk_pcie_setup_irq, +}; + static const struct of_device_id mtk_pcie_ids[] =3D { { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, + { .compatible =3D "econet,en7528-pcie", .data =3D &mtk_pcie_soc_en7528 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.39.5 From nobody Tue Apr 7 14:38:10 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E09CE3FB062; Thu, 12 Mar 2026 16:53:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773334432; cv=none; b=rSFpL6WlaZ1HmGcxO5M50l1SCRRgXnAO397hOg0W6yT9BduS6ncdltIeiEDBrOuBMBY1oUKzOB5vWZqi14ko94vIcYP0O3oNnEexZnqitds2UTPuZmdXcYWGogrdiDtO7I0tNlcrBfGX4HqeOA7Fyb1aAQD6B3cGwAAu+ALtXTs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773334432; c=relaxed/simple; bh=yVI7BzcMR6nQuCqFlO6Vo2NmSaC1XwkVm/81Bz/PFps=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZR/ku/icyHUXQHyWphF09JVDUDb/gBkgEhuA1XZMD3qxtaHgR8UhM0XqU7nVyxVRZW/sI5c7bm8zBEdfICFIlPAbfVJdfjTZOkNTApKqVqD8SuukAMcYgphasiB1UELzg9cgyfbYwF1tCgm4mBGrloxr/5Cw5u54y93CZF8H3xk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=l8A/OjO1; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="l8A/OjO1" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3CFE82C870D; Thu, 12 Mar 2026 17:53:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773334428; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Hun8qRSx+c81aOcVRS1X8gTZpBZdlow4lndHrL4U0TU=; b=l8A/OjO19AB3kGar5jy2BBZYBTLdZ7lVnXXpGFSz56etijPSpu4wle11E7UW/z1bTNeGGP VyllTeK0O611Ym3xdVvxt8SHI9Gz8GWcoTGTwj3retpeKTc1yJrPetAvzdDAZUXckThZxR aaZIb4N70qETFbUIP7qDzz1um6QGfyzrQLmAVBQ72v50smTnwl5Q7r7cFt9VlWAZG7nLQc 4w/Ee0no8N6EubpBSmdMCnBMlCLz5B6pBvWps6FXY4aZ+jlgpwfNbja92SyNlijW9AIjim fG4Wr9f575atj+GH6GRc9eFo6PIhMlmW81byoy/WXOu06DwaPz8CseuMQ1b/8Q== From: Caleb James DeLisle To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, ryder.lee@mediatek.com, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ansuelsmth@gmail.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle , Bjorn Helgaas Subject: [PATCH 3/3] PCI: Skip bridge window reads when window is not supported Date: Thu, 12 Mar 2026 16:53:32 +0000 Message-Id: <20260312165332.569772-4-cjd@cjdns.fr> In-Reply-To: <20260312165332.569772-1-cjd@cjdns.fr> References: <20260312165332.569772-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" pci_read_bridge_io() and pci_read_bridge_mmio_pref() read bridge window registers unconditionally. If the registers are hardwired to zero (not implemented), both base and limit will be 0. Since (0 <=3D 0) is true, a bogus window [mem 0x00000000-0x000fffff] or [io 0x0000-0x0fff] gets created. pci_read_bridge_windows() already detects unsupported windows by testing register writability and sets io_window/pref_window flags accordingly. Check these flags at the start of pci_read_bridge_io() and pci_read_bridge_mmio_pref() to skip reading registers when the window is not supported. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260113210259.GA715789@bhelgaas/ Signed-off-by: Ahmed Naseef Signed-off-by: Caleb James DeLisle --- drivers/pci/probe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index bccc7a4bdd79..4eacb741b4ec 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -395,6 +395,9 @@ static void pci_read_bridge_io(struct pci_dev *dev, str= uct resource *res, unsigned long io_mask, io_granularity, base, limit; struct pci_bus_region region; =20 + if (!dev->io_window) + return; + io_mask =3D PCI_IO_RANGE_MASK; io_granularity =3D 0x1000; if (dev->io_window_1k) { @@ -465,6 +468,9 @@ static void pci_read_bridge_mmio_pref(struct pci_dev *d= ev, struct resource *res, pci_bus_addr_t base, limit; struct pci_bus_region region; =20 + if (!dev->pref_window) + return; + pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); base64 =3D (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; --=20 2.39.5