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charset="utf-8" The exported-DMA path needs to describe each exposed descriptor window with the DMAEngine channel ID that owns it. Those IDs are only assigned once the channels have been registered. Cache the dma_chan IDs in dw_edma_chip after registration so controller frontends can later publish them as auxiliary-resource metadata without reaching back into the live channel objects. Signed-off-by: Koichiro Den --- drivers/dma/dw-edma/dw-edma-core.c | 18 +++++++++++++++++- include/linux/dma/edma.h | 4 ++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index cd34a3ea602d..a13beacce2e7 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -837,6 +837,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) struct dma_device *dma; u32 i, ch_cnt; u32 pos; + int ret; =20 ch_cnt =3D dw->wr_ch_cnt + dw->rd_ch_cnt; dma =3D &dw->dma; @@ -932,7 +933,22 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u= 32 wr_alloc, u32 rd_alloc) dma_set_max_seg_size(dma->dev, U32_MAX); =20 /* Register DMA device */ - return dma_async_device_register(dma); + ret =3D dma_async_device_register(dma); + if (ret) + return ret; + + /* Cache dma_chan.id in dw_edma_chip */ + for (i =3D 0; i < ch_cnt; i++) { + chan =3D &dw->chan[i]; + + if (i < dw->wr_ch_cnt) + chip->chan_ids_wr[i] =3D chan->vc.chan.chan_id; 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charset="utf-8" A peer-visible DMA descriptor window needs a little more context than just address and size. In particular, a generic consumer needs to know which DMAEngine channel it belongs to and in which direction that channel operates. Extend struct pci_epc_aux_resource with dma_chan metadata for PCI_EPC_AUX_DMA_CHAN_DESC resources so controllers can expose that information in a uniform way. Signed-off-by: Koichiro Den --- include/linux/pci-epc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index d6b0a0833e9f..7dd2e4d5d952 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -78,6 +78,11 @@ enum pci_epc_aux_resource_type { PCI_EPC_AUX_DOORBELL_MMIO, }; =20 +enum pci_epc_aux_dma_dir { + PCI_EPC_AUX_DMA_DIR_READ =3D 0, + PCI_EPC_AUX_DMA_DIR_WRITE =3D 1, +}; + /** * struct pci_epc_aux_resource - a physical auxiliary resource that may be * exposed for peer use @@ -103,6 +108,13 @@ struct pci_epc_aux_resource { int irq; /* IRQ number for the doorbell handler */ u32 data; /* write value to ring the doorbell */ } db_mmio; + + /* PCI_EPC_AUX_DMA_CHAN_DESC */ + struct { + int chan_id; + u8 dir; + u8 reserved[3]; + } dma_chan; } u; }; =20 --=20 2.51.0 From nobody Tue Apr 7 14:41:19 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11021104.outbound.protection.outlook.com [40.107.74.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF0E03932D1; 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charset="utf-8" DesignWare endpoint controllers already expose the controller MMIO region and the per-channel linked-list descriptor windows as auxiliary resources. Populate the new DMA channel metadata for each PCI_EPC_AUX_DMA_CHAN_DESC entry using the cached channel IDs and channel direction. This lets generic consumers match delegated DMA channels to the descriptor windows they need to program. Signed-off-by: Koichiro Den --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index eec20800a745..1e584f6a6565 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -947,6 +947,10 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 f= unc_no, u8 vfunc_no, .size =3D edma->ll_region_wr[i].sz, .bar =3D NO_BAR, .bar_offset =3D 0, + .u.dma_chan =3D { + .chan_id =3D edma->chan_ids_wr[i], + .dir =3D PCI_EPC_AUX_DMA_DIR_WRITE, + }, }; } =20 @@ -961,6 +965,10 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 f= unc_no, u8 vfunc_no, .size =3D edma->ll_region_rd[i].sz, .bar =3D NO_BAR, .bar_offset =3D 0, + .u.dma_chan =3D { + .chan_id =3D edma->chan_ids_rd[i], + .dir =3D PCI_EPC_AUX_DMA_DIR_READ, + }, }; } =20 --=20 2.51.0 From nobody Tue Apr 7 14:41:19 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11021077.outbound.protection.outlook.com [52.101.125.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36D853F99CD; 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charset="utf-8" DesignWare endpoint eDMA can signal completion both locally and remotely through LIE/RIE. A remotely controlled channel needs a per-channel policy for whether completions are handled locally, remotely, or both; otherwise the endpoint and host can race to acknowledge the interrupt. Add dw_edma_peripheral_config, carried through dma_slave_config, to let a frontend select the interrupt routing mode for each channel. Update the v0 programming path so linked-list interrupt generation and DONE/ABORT masking follow the selected mode. If a frontend does nothing, the default keeps the existing behavior. For now reject the new peripheral_config on HDMA, where the routing model has not been implemented or validated yet, instead of silently misprogramming interrupts. Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/dma/dw-edma/dw-edma-core.c | 55 +++++++++++++++++++++++++++ drivers/dma/dw-edma/dw-edma-core.h | 13 +++++++ drivers/dma/dw-edma/dw-edma-v0-core.c | 26 +++++++++---- include/linux/dma/edma.h | 38 ++++++++++++++++++ 4 files changed, 124 insertions(+), 8 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index a13beacce2e7..6341bda4c303 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -219,11 +219,60 @@ static void dw_edma_device_caps(struct dma_chan *dcha= n, } } =20 +static enum dw_edma_ch_irq_mode +dw_edma_get_default_irq_mode(struct dw_edma_chan *chan) +{ + switch (chan->dw->chip->default_irq_mode) { + case DW_EDMA_CH_IRQ_DEFAULT: + case DW_EDMA_CH_IRQ_LOCAL: + case DW_EDMA_CH_IRQ_REMOTE: + return chan->dw->chip->default_irq_mode; + default: + return DW_EDMA_CH_IRQ_DEFAULT; + } +} + +static int dw_edma_parse_irq_mode(struct dw_edma_chan *chan, + const struct dma_slave_config *config, + enum dw_edma_ch_irq_mode *mode) +{ + const struct dw_edma_peripheral_config *pcfg; + + /* peripheral_config is optional, fall back to the frontend default. */ + *mode =3D dw_edma_get_default_irq_mode(chan); + if (!config || !config->peripheral_config) + return 0; + + if (chan->dw->chip->mf =3D=3D EDMA_MF_HDMA_NATIVE) + return -EOPNOTSUPP; + + if (config->peripheral_size < sizeof(*pcfg)) + return -EINVAL; + + pcfg =3D config->peripheral_config; + switch (pcfg->irq_mode) { + case DW_EDMA_CH_IRQ_DEFAULT: + case DW_EDMA_CH_IRQ_LOCAL: + case DW_EDMA_CH_IRQ_REMOTE: + *mode =3D pcfg->irq_mode; + return 0; + default: + return -EINVAL; + } +} + static int dw_edma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + enum dw_edma_ch_irq_mode mode; + int ret; =20 + ret =3D dw_edma_parse_irq_mode(chan, config, &mode); + if (ret) + return ret; + + chan->irq_mode =3D mode; memcpy(&chan->config, config, sizeof(*config)); chan->configured =3D true; =20 @@ -808,11 +857,14 @@ static int dw_edma_alloc_chan_resources(struct dma_ch= an *dchan) if (chan->status !=3D EDMA_ST_IDLE) return -EBUSY; =20 + chan->irq_mode =3D dw_edma_get_default_irq_mode(chan); + return 0; } =20 static void dw_edma_free_chan_resources(struct dma_chan *dchan) { + struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); unsigned long timeout =3D jiffies + msecs_to_jiffies(5000); int ret; =20 @@ -826,6 +878,8 @@ static void dw_edma_free_chan_resources(struct dma_chan= *dchan) =20 cpu_relax(); } + + chan->irq_mode =3D dw_edma_get_default_irq_mode(chan); } =20 static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_= alloc) @@ -860,6 +914,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) chan->configured =3D false; chan->request =3D EDMA_REQ_NONE; chan->status =3D EDMA_ST_IDLE; + chan->irq_mode =3D dw_edma_get_default_irq_mode(chan); =20 if (chan->dir =3D=3D EDMA_DIR_WRITE) chan->ll_max =3D (chip->ll_region_wr[chan->id].sz / EDMA_LL_SZ); diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 59b24973fa7d..e021551b0b9f 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -81,6 +81,8 @@ struct dw_edma_chan { =20 struct msi_msg msi; =20 + enum dw_edma_ch_irq_mode irq_mode; + enum dw_edma_request request; enum dw_edma_status status; u8 configured; @@ -223,4 +225,15 @@ dw_edma_core_db_offset(struct dw_edma *dw) return dw->core->db_offset(dw); } =20 +static inline bool +dw_edma_core_ch_ignore_irq(struct dw_edma_chan *chan) +{ + struct dw_edma *dw =3D chan->dw; + + if (dw->chip->flags & DW_EDMA_CHIP_LOCAL) + return chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE; + else + return chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_LOCAL; +} + #endif /* _DW_EDMA_CORE_H */ diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw= -edma-v0-core.c index 69e8279adec8..2e95da0d6fc2 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -256,8 +256,10 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq,= enum dw_edma_dir dir, for_each_set_bit(pos, &val, total) { chan =3D &dw->chan[pos + off]; =20 - dw_edma_v0_core_clear_done_int(chan); - done(chan); + if (!dw_edma_core_ch_ignore_irq(chan)) { + dw_edma_v0_core_clear_done_int(chan); + done(chan); + } =20 ret =3D IRQ_HANDLED; } @@ -267,8 +269,10 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq,= enum dw_edma_dir dir, for_each_set_bit(pos, &val, total) { chan =3D &dw->chan[pos + off]; =20 - dw_edma_v0_core_clear_abort_int(chan); - abort(chan); + if (!dw_edma_core_ch_ignore_irq(chan)) { + dw_edma_v0_core_clear_abort_int(chan); + abort(chan); + } =20 ret =3D IRQ_HANDLED; } @@ -331,7 +335,8 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_= chunk *chunk) j--; if (!j) { control |=3D DW_EDMA_V0_LIE; - if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) && + chan->irq_mode !=3D DW_EDMA_CH_IRQ_LOCAL) control |=3D DW_EDMA_V0_RIE; } =20 @@ -407,10 +412,15 @@ static void dw_edma_v0_core_start(struct dw_edma_chun= k *chunk, bool first) break; } } - /* Interrupt unmask - done, abort */ + /* Interrupt mask/unmask - done, abort */ tmp =3D GET_RW_32(dw, chan->dir, int_mask); - tmp &=3D ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); - tmp &=3D ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); + if (chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE) { + tmp |=3D FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); + tmp |=3D FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); + } else { + tmp &=3D ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); + tmp &=3D ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); + } SET_RW_32(dw, chan->dir, int_mask, tmp); /* Linked list error */ tmp =3D GET_RW_32(dw, chan->dir, linked_list_err_en); diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 0b861e8d305e..e4a6302bd04c 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -60,6 +60,41 @@ enum dw_edma_chip_flags { DW_EDMA_CHIP_LOCAL =3D BIT(0), }; =20 +/** + * enum dw_edma_ch_irq_mode - per-channel interrupt routing control + * @DW_EDMA_CH_IRQ_DEFAULT: keep legacy behavior + * @DW_EDMA_CH_IRQ_LOCAL: local interrupt only (edma_int[]) + * @DW_EDMA_CH_IRQ_REMOTE: remote interrupt only (IMWr/MSI), + * while masking local DONE/ABORT output. + * + * DesignWare EP eDMA can signal interrupts locally through the edma_int[] + * bus, and remotely using posted memory writes (IMWr) that may be + * interpreted as MSI/MSI-X by the RC. + * + * DMA_*_INT_MASK gates the local edma_int[] assertion, while there is no + * dedicated per-channel mask for IMWr generation. To request a remote-only + * interrupt, Synopsys recommends setting both LIE and RIE, and masking the + * local interrupt in DMA_*_INT_MASK (rather than relying on LIE=3D0/RIE= =3D1). + * See the DesignWare endpoint databook 5.40a, Non Linked List Mode + * interrupt handling ("Hint"). + */ +enum dw_edma_ch_irq_mode { + DW_EDMA_CH_IRQ_DEFAULT =3D 0, + DW_EDMA_CH_IRQ_LOCAL, + DW_EDMA_CH_IRQ_REMOTE, +}; + +/** + * struct dw_edma_peripheral_config - dw-edma specific slave configuration + * @irq_mode: per-channel interrupt routing control. + * + * Pass this structure via dma_slave_config.peripheral_config and + * dma_slave_config.peripheral_size. + */ +struct dw_edma_peripheral_config { + enum dw_edma_ch_irq_mode irq_mode; +}; + /** * struct dw_edma_chip - representation of DesignWare eDMA controller hard= ware * @dev: struct device of the eDMA controller @@ -76,6 +111,8 @@ enum dw_edma_chip_flags { * @db_irq: Virtual IRQ dedicated to interrupt emulation * @db_offset: Offset from DMA register base * @mf: DMA register map format + * @default_irq_mode: default per-channel interrupt routing when client + * does not supply dw_edma_peripheral_config * @dw: struct dw_edma that is filled by dw_edma_probe() */ struct dw_edma_chip { @@ -105,6 +142,7 @@ struct dw_edma_chip { int chan_ids_rd[EDMA_MAX_RD_CH]; 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charset="utf-8" dw-edma caches the MSI/MSI-X message programmed into each channel so the controller can generate IMWr interrupts for completed transfers. Today that message is built inline while dw-edma requests its IRQs and implicitly assumes that the allocated vectors belong to dw-edma itself only. That becomes fragile once another frontend also requests IRQs from chip->dev and dw-edma still needs to derive the right MSI data value for its own vectors. Factor the logic into a helper that composes the MSI message from the allocated IRQ number and the owning device. For multi-vector MSI, derive the per-vector data value relative to msi_get_virq(dev, 0) instead of assuming a dw-edma-private vector block. No functional change intended for existing users. Signed-off-by: Koichiro Den --- drivers/dma/dw-edma/dw-edma-core.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 6341bda4c303..c404248767e8 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -1020,6 +1020,28 @@ static inline void dw_edma_add_irq_mask(u32 *mask, u= 32 alloc, u16 cnt) (*mask)++; } =20 +static void dw_edma_compose_msi(struct device *dev, int irq, struct msi_ms= g *out) +{ + struct msi_desc *desc =3D irq_get_msi_desc(irq); + struct msi_msg msg; + unsigned int base; + + if (!desc) + return; + + get_cached_msi_msg(irq, &msg); + if (!desc->pci.msi_attrib.is_msix) { + /* + * For multi-vector MSI, the cached message corresponds to + * vector 0. Adjust msg.data by the IRQ index so that each + * vector gets a unique MSI data value for IMWr Data Register. + */ + base =3D msi_get_virq(dev, 0); + msg.data +=3D (irq - base); + } + *out =3D msg; +} + static int dw_edma_irq_request(struct dw_edma *dw, u32 *wr_alloc, u32 *rd_alloc) { @@ -1050,8 +1072,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } =20 - if (irq_get_msi_desc(irq)) - get_cached_msi_msg(irq, &dw->irq[0].msi); + dw_edma_compose_msi(dev, irq, &dw->irq[0].msi); =20 dw->nr_irqs =3D 1; } else { @@ -1077,8 +1098,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, if (err) goto err_irq_free; =20 - if (irq_get_msi_desc(irq)) - get_cached_msi_msg(irq, &dw->irq[i].msi); + dw_edma_compose_msi(dev, irq, &dw->irq[i].msi); } =20 dw->nr_irqs =3D i; --=20 2.51.0 From nobody Tue Apr 7 14:41:19 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11021104.outbound.protection.outlook.com [40.107.74.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 507593FBEBF; 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charset="utf-8" The next patches add per-memory-window offsets, shared BAR placement, and optional DMA export state. Keeping per-window state in parallel arrays would make that work noisy and error-prone. Group the runtime memory-window state into struct epf_ntb_mw so follow-up changes can extend a single object instead of touching multiple arrays. No functional change intended. Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 42 ++++++++++--------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index bd9a3380a537..16656659a9ce 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -128,6 +128,12 @@ struct epf_ntb_ctrl { u32 db_offset[MAX_DB_COUNT]; } __packed; =20 +struct epf_ntb_mw { + u64 size; + phys_addr_t vpci_mw_phys; + void __iomem *vpci_mw_addr; +}; + struct epf_ntb { struct ntb_dev ntb; struct pci_epf *epf; @@ -136,7 +142,7 @@ struct epf_ntb { u32 num_mws; u32 db_count; u32 spad_count; - u64 mws_size[MAX_MW]; + struct epf_ntb_mw mw[MAX_MW]; atomic64_t db; atomic64_t peer_db_pending; struct work_struct peer_db_work; @@ -159,9 +165,6 @@ struct epf_ntb { =20 u32 *epf_db; =20 - phys_addr_t vpci_mw_phy[MAX_MW]; - void __iomem *vpci_mw_addr[MAX_MW]; - struct delayed_work cmd_handler; }; =20 @@ -227,7 +230,7 @@ static int epf_ntb_configure_mw(struct epf_ntb *ntb, u3= 2 mw) u64 addr, size; int ret =3D 0; =20 - phys_addr =3D ntb->vpci_mw_phy[mw]; + phys_addr =3D ntb->mw[mw].vpci_mw_phys; addr =3D ntb->reg->addr; size =3D ntb->reg->size; =20 @@ -254,7 +257,7 @@ static void epf_ntb_teardown_mw(struct epf_ntb *ntb, u3= 2 mw) pci_epc_unmap_addr(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, - ntb->vpci_mw_phy[mw]); + ntb->mw[mw].vpci_mw_phys); } =20 /** @@ -763,7 +766,7 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) struct device *dev =3D &ntb->epf->dev; =20 for (i =3D 0; i < ntb->num_mws; i++) { - size =3D ntb->mws_size[i]; + size =3D ntb->mw[i].size; barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; =20 ntb->epf->bar[barno].barno =3D barno; @@ -784,10 +787,11 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) } =20 /* Allocate EPC outbound memory windows to vpci vntb device */ - ntb->vpci_mw_addr[i] =3D pci_epc_mem_alloc_addr(ntb->epf->epc, - &ntb->vpci_mw_phy[i], - size); - if (!ntb->vpci_mw_addr[i]) { + ntb->mw[i].vpci_mw_addr =3D + pci_epc_mem_alloc_addr(ntb->epf->epc, + &ntb->mw[i].vpci_mw_phys, + size); + if (!ntb->mw[i].vpci_mw_addr) { ret =3D -ENOMEM; dev_err(dev, "Failed to allocate source address\n"); goto err_set_bar; @@ -824,9 +828,9 @@ static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, i= nt num_mws) &ntb->epf->bar[barno]); =20 pci_epc_mem_free_addr(ntb->epf->epc, - ntb->vpci_mw_phy[i], - ntb->vpci_mw_addr[i], - ntb->mws_size[i]); + ntb->mw[i].vpci_mw_phys, + ntb->mw[i].vpci_mw_addr, + ntb->mw[i].size); } } =20 @@ -1065,7 +1069,7 @@ static ssize_t epf_ntb_##_name##_show(struct config_i= tem *item, \ return -ERANGE; \ } \ idx =3D array_index_nospec(idx, ntb->num_mws); \ - return sprintf(page, "%llu\n", ntb->mws_size[idx]); \ + return sprintf(page, "%llu\n", ntb->mw[idx].size); \ } =20 #define EPF_NTB_MW_W(_name) \ @@ -1093,7 +1097,7 @@ static ssize_t epf_ntb_##_name##_store(struct config_= item *item, \ return -ERANGE; \ } \ idx =3D array_index_nospec(idx, ntb->num_mws); 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charset="utf-8" Add EPC ops and core wrappers to delegate and undelegate controller-owned DMA channels. The exported DMA helper needs more than a passive "delegated" bitmap: it must be able to reserve channels away from local users, let the backend perform controller-specific setup (e.g. prevent the EP from racing to ack the completion interrupt for delegated channels), and later hand the channels back as a matched lifetime operation. Signed-off-by: Koichiro Den --- drivers/pci/endpoint/pci-epc-core.c | 84 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 19 +++++++ 2 files changed, 103 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index dc6d6ab4ea1e..892f7ccbd236 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -197,6 +197,90 @@ int pci_epc_get_aux_resources(struct pci_epc *epc, u8 = func_no, u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_get_aux_resources); =20 +/** + * pci_epc_delegate_dma_channels() - reserve EPC-owned DMA channels + * @epc: EPC device + * @func_no: function number + * @vfunc_no: virtual function number + * @dir: DMA channel direction + * @req_chans: number of channels requested + * @chan_ids: output array of delegated channel IDs + * @max_chans: capacity of @chan_ids in entries + * + * Return: + * * > 0: number of channels delegated + * * -EOPNOTSUPP: backend does not support DMA delegation + * * other -errno on failure + */ +int pci_epc_delegate_dma_channels(struct pci_epc *epc, u8 func_no, u8 vfun= c_no, + enum pci_epc_aux_dma_dir dir, + u32 req_chans, int *chan_ids, u32 max_chans) +{ + int ret; + + if (!epc || !epc->ops) + return -EINVAL; + + if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + return -EINVAL; + + if (!req_chans || !chan_ids || !max_chans) + return -EINVAL; + + if (!epc->ops->delegate_dma_channels) + return -EOPNOTSUPP; + + mutex_lock(&epc->lock); + ret =3D epc->ops->delegate_dma_channels(epc, func_no, vfunc_no, dir, + req_chans, chan_ids, max_chans); + mutex_unlock(&epc->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_epc_delegate_dma_channels); + +/** + * pci_epc_undelegate_dma_channels() - release previously delegated channe= ls + * @epc: EPC device + * @func_no: function number + * @vfunc_no: virtual function number + * @dir: DMA channel direction + * @chan_ids: array of delegated channel IDs + * @num_chans: number of entries in @chan_ids + * + * Return: 0 on success, negative errno otherwise. + */ +int pci_epc_undelegate_dma_channels(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, + enum pci_epc_aux_dma_dir dir, + const int *chan_ids, u32 num_chans) +{ + int ret; + + if (!epc || !epc->ops) + return -EINVAL; + + if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + return -EINVAL; + + if (!num_chans) + return 0; + + if (!chan_ids) + return -EINVAL; + + if (!epc->ops->undelegate_dma_channels) + return -EOPNOTSUPP; + + mutex_lock(&epc->lock); + ret =3D epc->ops->undelegate_dma_channels(epc, func_no, vfunc_no, dir, + chan_ids, num_chans); + mutex_unlock(&epc->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_epc_undelegate_dma_channels); + /** * pci_epc_stop() - stop the PCI link * @epc: the link of the EPC device that has to be stopped diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 7dd2e4d5d952..db8623b84c56 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -142,6 +142,8 @@ struct pci_epc_aux_resource { * @stop: ops to stop the PCI link * @get_features: ops to get the features supported by the EPC * @get_aux_resources: ops to retrieve controller-owned auxiliary resources + * @delegate_dma_channels: reserve controller-owned DMA channels for peer = use + * @undelegate_dma_channels: release previously delegated DMA channels * @owner: the module owner containing the ops */ struct pci_epc_ops { @@ -176,6 +178,16 @@ struct pci_epc_ops { int (*get_aux_resources)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epc_aux_resource *resources, int num_resources); + int (*delegate_dma_channels)(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, + enum pci_epc_aux_dma_dir dir, + u32 req_chans, int *chan_ids, + u32 max_chans); + int (*undelegate_dma_channels)(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, + enum pci_epc_aux_dma_dir dir, + const int *chan_ids, + u32 num_chans); struct module *owner; }; =20 @@ -403,6 +415,13 @@ const struct pci_epc_features *pci_epc_get_features(st= ruct pci_epc *epc, int pci_epc_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epc_aux_resource *resources, int num_resources); +int pci_epc_delegate_dma_channels(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, enum pci_epc_aux_dma_dir dir, + u32 req_chans, int *chan_ids, u32 max_chans); +int pci_epc_undelegate_dma_channels(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, + enum pci_epc_aux_dma_dir dir, + const int *chan_ids, u32 num_chans); enum pci_barno pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features --=20 2.51.0 From nobody Tue Apr 7 14:41:20 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11020091.outbound.protection.outlook.com [52.101.229.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB8B33FCB04; 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charset="utf-8" Implement the new EPC DMA delegation hooks for DesignWare endpoint controllers with integrated eDMA. The DWC implementation requests channels through DMAEngine, programs DW_EDMA_CH_IRQ_REMOTE while the channels are delegated, and keeps the struct dma_chan references in endpoint-private state so the reservation is maintained until undelegation. When the channels are returned, restore the default IRQ mode before releasing them back to DMAEngine. Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 188 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 11 + 2 files changed, 199 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 1e584f6a6565..4c997cf1989c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -818,6 +818,192 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_= no, u8 vfunc_no) return ep->ops->get_features(ep); } =20 +struct dw_pcie_ep_dma_filter { + struct device *dma_dev; + u32 direction; +}; + +static int +dw_pcie_ep_dma_dir_to_direction(enum pci_epc_aux_dma_dir dir, u32 *directi= on) +{ + switch (dir) { + case PCI_EPC_AUX_DMA_DIR_READ: + *direction =3D BIT(DMA_DEV_TO_MEM); + return 0; + case PCI_EPC_AUX_DMA_DIR_WRITE: + *direction =3D BIT(DMA_MEM_TO_DEV); + return 0; + default: + return -EINVAL; + } +} + +static bool dw_pcie_ep_dma_filter_fn(struct dma_chan *chan, void *arg) +{ + struct dma_slave_caps caps; + struct dw_pcie_ep_dma_filter *filter =3D arg; + int ret; + + if (chan->device->dev !=3D filter->dma_dev) + return false; + + ret =3D dma_get_slave_caps(chan, &caps); + if (ret < 0) + return false; + + return !!(caps.directions & filter->direction); +} + +static int dw_pcie_ep_dma_set_irq_mode(struct dma_chan *chan, + enum dw_edma_ch_irq_mode mode) +{ + struct dw_edma_peripheral_config pcfg =3D { + .irq_mode =3D mode, + }; + struct dma_slave_config cfg =3D { + .peripheral_config =3D &pcfg, + .peripheral_size =3D sizeof(pcfg), + }; + + return dmaengine_slave_config(chan, &cfg); +} + +static struct dw_pcie_ep_dma_delegated_chan * +dw_pcie_ep_find_delegated_dma_chan(struct dw_pcie_ep *ep, + enum pci_epc_aux_dma_dir dir, int chan_id) +{ + unsigned int i; + + for (i =3D 0; i < ep->num_delegated_dma_chans; i++) { + if (ep->delegated_dma_chans[i].dir !=3D dir) + continue; + if (ep->delegated_dma_chans[i].chan_id !=3D chan_id) + continue; + return &ep->delegated_dma_chans[i]; + } + + return NULL; +} + +static void +dw_pcie_ep_remove_delegated_dma_chan(struct dw_pcie_ep *ep, + struct dw_pcie_ep_dma_delegated_chan *dchan) +{ + unsigned int idx =3D dchan - ep->delegated_dma_chans; + + if (idx >=3D ep->num_delegated_dma_chans) + return; + + ep->num_delegated_dma_chans--; + if (idx !=3D ep->num_delegated_dma_chans) + ep->delegated_dma_chans[idx] =3D + ep->delegated_dma_chans[ep->num_delegated_dma_chans]; + + memset(&ep->delegated_dma_chans[ep->num_delegated_dma_chans], 0, + sizeof(ep->delegated_dma_chans[0])); +} + +static int +dw_pcie_ep_undelegate_dma_channels(struct pci_epc *epc, u8 func_no, u8 vfu= nc_no, + enum pci_epc_aux_dma_dir dir, + const int *chan_ids, u32 num_chans) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie_ep_dma_delegated_chan *dchan; + int ret, rc =3D 0; + u32 i; + + for (i =3D 0; i < num_chans; i++) { + dchan =3D dw_pcie_ep_find_delegated_dma_chan(ep, dir, chan_ids[i]); + if (!dchan) { + if (!rc) + rc =3D -ENOENT; + continue; + } + + ret =3D dw_pcie_ep_dma_set_irq_mode(dchan->chan, + DW_EDMA_CH_IRQ_DEFAULT); + if (ret && !rc) + rc =3D ret; + + dma_release_channel(dchan->chan); + dw_pcie_ep_remove_delegated_dma_chan(ep, dchan); + } + + return rc; +} + +static int +dw_pcie_ep_delegate_dma_channels(struct pci_epc *epc, u8 func_no, u8 vfunc= _no, + enum pci_epc_aux_dma_dir dir, + u32 req_chans, int *chan_ids, u32 max_chans) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + struct dw_pcie_ep_dma_filter filter; + dma_cap_mask_t dma_mask; + struct dma_chan *chan; + u32 delegated =3D 0; + u32 direction; + int ret; + + ret =3D dw_pcie_ep_dma_dir_to_direction(dir, &direction); + if (ret) + return ret; + + if (!pci->edma.dev) + return -ENODEV; + + /* Limit to integrated DMA engine */ + filter.dma_dev =3D pci->edma.dev; + filter.direction =3D direction; + + dma_cap_zero(dma_mask); + dma_cap_set(DMA_SLAVE, dma_mask); + + ret =3D -ENODEV; + while (delegated < req_chans && delegated < max_chans) { + if (ep->num_delegated_dma_chans >=3D + ARRAY_SIZE(ep->delegated_dma_chans)) { + ret =3D -ENOSPC; + break; + } + + chan =3D dma_request_channel(dma_mask, dw_pcie_ep_dma_filter_fn, + &filter); + if (!chan) + break; + + ret =3D dw_pcie_ep_dma_set_irq_mode(chan, DW_EDMA_CH_IRQ_REMOTE); + if (ret) { + dma_release_channel(chan); + goto err_release; + } + + if (chan->chan_id < 0) { + dma_release_channel(chan); + ret =3D -ERANGE; + goto err_release; + } + + ep->delegated_dma_chans[ep->num_delegated_dma_chans++] =3D + (struct dw_pcie_ep_dma_delegated_chan) { + .chan =3D chan, + .chan_id =3D chan->chan_id, + .dir =3D dir, + }; + chan_ids[delegated++] =3D chan->chan_id; + } + + return delegated ? : ret; + +err_release: + dw_pcie_ep_undelegate_dma_channels(epc, func_no, vfunc_no, dir, + chan_ids, delegated); + + return ret; +} + static const struct pci_epc_bar_rsvd_region * dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep, enum pci_epc_bar_rsvd_region_type type, @@ -991,6 +1177,8 @@ static const struct pci_epc_ops epc_ops =3D { .stop =3D dw_pcie_ep_stop, .get_features =3D dw_pcie_ep_get_features, .get_aux_resources =3D dw_pcie_ep_get_aux_resources, + .delegate_dma_channels =3D dw_pcie_ep_delegate_dma_channels, + .undelegate_dma_channels =3D dw_pcie_ep_undelegate_dma_channels, }; =20 /** diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 52f26663e8b1..d7d60278fbba 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -479,6 +479,12 @@ struct dw_pcie_ep_func { unsigned int num_ib_atu_indexes[PCI_STD_NUM_BARS]; }; =20 +struct dw_pcie_ep_dma_delegated_chan { + struct dma_chan *chan; + int chan_id; + u8 dir; +}; + struct dw_pcie_ep { struct pci_epc *epc; struct list_head func_list; @@ -496,6 +502,11 @@ struct dw_pcie_ep { bool msi_iatu_mapped; u64 msi_msg_addr; size_t msi_map_size; + + /* DMA channels reserved for peer export */ + u8 num_delegated_dma_chans; + struct dw_pcie_ep_dma_delegated_chan + delegated_dma_chans[EDMA_MAX_WR_CH + EDMA_MAX_RD_CH]; }; =20 struct dw_pcie_ops { --=20 2.51.0 From nobody Tue Apr 7 14:41:20 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11021104.outbound.protection.outlook.com [40.107.74.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11F83FB7DE; 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charset="utf-8" Add a generic helper that packages controller-owned DMA resources into a peer-visible BAR slice described by exported DMA ABI v1. pci_epf_alloc_dma() queries EPC auxiliary resources, delegates the requested DMA read channels, builds an ABI header in coherent memory, and assembles the BAR region list covering the header, controller register window, and per-channel descriptor windows. If the controller control window is not already BAR-backed, map it into the exported slice so the peer still sees a self-contained layout. The first ABI is designed based on the DesignWare unrolled eDMA model, but it is intended to be vendor-neutral. It exports delegated READ channels only, which are the channels the host uses to send data from host memory into the endpoint. Signed-off-by: Koichiro Den --- drivers/pci/endpoint/Makefile | 2 +- drivers/pci/endpoint/pci-ep-dma.c | 342 ++++++++++++++++++++++++++++++ include/linux/pci-ep-dma.h | 130 ++++++++++++ 3 files changed, 473 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/endpoint/pci-ep-dma.c create mode 100644 include/linux/pci-ep-dma.h diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile index b4869d52053a..94824f3ed5a1 100644 --- a/drivers/pci/endpoint/Makefile +++ b/drivers/pci/endpoint/Makefile @@ -5,5 +5,5 @@ =20 obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS) +=3D pci-ep-cfs.o obj-$(CONFIG_PCI_ENDPOINT) +=3D pci-epc-core.o pci-epf-core.o\ - pci-epc-mem.o functions/ + pci-epc-mem.o pci-ep-dma.o functions/ obj-$(CONFIG_PCI_ENDPOINT_MSI_DOORBELL) +=3D pci-ep-msi.o diff --git a/drivers/pci/endpoint/pci-ep-dma.c b/drivers/pci/endpoint/pci-e= p-dma.c new file mode 100644 index 000000000000..2a996f9b1424 --- /dev/null +++ b/drivers/pci/endpoint/pci-ep-dma.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Generic exported DMA helper for PCI endpoint functions + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct pci_epc_aux_resource * +pci_ep_dma_find_ctrl(const struct pci_epc_aux_resource *resources, int cou= nt) +{ + int i; + + for (i =3D 0; i < count; i++) + if (resources[i].type =3D=3D PCI_EPC_AUX_DMA_CTRL_MMIO) + return &resources[i]; + + return NULL; +} + +static const struct pci_epc_aux_resource * +pci_ep_dma_find_desc(const struct pci_epc_aux_resource *resources, int cou= nt, + int chan_id) +{ + int i; + + /* + * ABI v1 exports delegated READ channels only. A remote client uses + * those channels to pull host memory into the endpoint, so ignore WRITE + * channel descriptors here. + */ + for (i =3D 0; i < count; i++) { + if (resources[i].type !=3D PCI_EPC_AUX_DMA_CHAN_DESC) + continue; + if (resources[i].u.dma_chan.dir !=3D PCI_EPC_AUX_DMA_DIR_READ) + continue; + if (resources[i].u.dma_chan.chan_id !=3D chan_id) + continue; + return &resources[i]; + } + + return NULL; +} + +static int pci_ep_dma_undelegate_chans(struct pci_epf *epf, const int *cha= n_ids, + u32 num_chans) +{ + if (!num_chans) + return 0; + + return pci_epc_undelegate_dma_channels(epf->epc, epf->func_no, + epf->vfunc_no, + PCI_EPC_AUX_DMA_DIR_READ, + chan_ids, num_chans); +} + +static int pci_ep_dma_map_resource(struct device *dev, phys_addr_t phys, + size_t size, size_t align, + dma_addr_t *dma_addr, size_t *map_size, + u32 *map_delta) +{ + phys_addr_t base; + size_t map_align; + + map_align =3D max_t(size_t, PAGE_SIZE, align); + base =3D ALIGN_DOWN(phys, map_align); + *map_delta =3D phys - base; + *map_size =3D ALIGN(size + *map_delta, map_align); + *dma_addr =3D dma_map_resource(dev, base, *map_size, + DMA_BIDIRECTIONAL, 0); + if (dma_mapping_error(dev, *dma_addr)) + return -ENOMEM; + + return 0; +} + +struct pci_ep_dma *pci_epf_alloc_dma(struct pci_epf *epf, enum pci_barno b= ar, + u32 offset, u32 req_chans) +{ + const struct pci_epc_aux_resource *descs[PCI_EP_DMA_MAX_CHANS] =3D { }; + const struct pci_epc_features *epc_features; + int chan_ids[PCI_EP_DMA_MAX_CHANS] =3D { 0 }; + int kept_chan_ids[PCI_EP_DMA_MAX_CHANS] =3D { 0 }; + int rejected_chan_ids[PCI_EP_DMA_MAX_CHANS] =3D { 0 }; + const struct pci_epc_aux_resource *ctrl; + struct pci_epc_aux_resource *res =3D NULL; + struct pci_ep_dma_hdr_v1 *hdr; + size_t align, hdr_sz, cur; + unsigned int delegated_chans =3D 0; + unsigned int rejected_chans =3D 0; + unsigned int num_chans =3D 0; + struct pci_ep_dma *dma; + struct device *dma_dev; + struct pci_epc *epc; + int count, ret; + unsigned int i; + + if (!epf || !epf->epc) + return ERR_PTR(-EINVAL); + + epc =3D epf->epc; + epc_features =3D pci_epc_get_features(epc, epf->func_no, epf->vfunc_no); + if (!epc_features) + return ERR_PTR(-ENODEV); + + count =3D pci_epc_get_aux_resources(epc, epf->func_no, epf->vfunc_no, + NULL, 0); + if (count < 0) + return ERR_PTR(count); + + res =3D kcalloc(count, sizeof(*res), GFP_KERNEL); + if (!res) + return ERR_PTR(-ENOMEM); + + ret =3D pci_epc_get_aux_resources(epc, epf->func_no, epf->vfunc_no, + res, count); + if (ret < 0) + goto err_free_res; + count =3D ret; + + ret =3D pci_epc_delegate_dma_channels(epc, epf->func_no, epf->vfunc_no, + PCI_EPC_AUX_DMA_DIR_READ, + max_t(u32, 1, req_chans), + chan_ids, + ARRAY_SIZE(chan_ids)); + if (ret < 0) + goto err_free_res; + delegated_chans =3D ret; + + ctrl =3D pci_ep_dma_find_ctrl(res, count); + if (!ctrl) { + ret =3D -ENODEV; + goto err_undelegate; + } + + for (i =3D 0; i < delegated_chans; i++) { + const struct pci_epc_aux_resource *desc; + + desc =3D pci_ep_dma_find_desc(res, count, chan_ids[i]); + if (!desc) { + rejected_chan_ids[rejected_chans++] =3D chan_ids[i]; + continue; + } + + descs[num_chans] =3D desc; + kept_chan_ids[num_chans++] =3D chan_ids[i]; + } + + ret =3D pci_ep_dma_undelegate_chans(epf, rejected_chan_ids, rejected_chan= s); + if (ret) + goto err_undelegate; + memcpy(chan_ids, kept_chan_ids, num_chans * sizeof(chan_ids[0])); + delegated_chans =3D num_chans; + + if (!num_chans) { + ret =3D -ENODEV; + goto err_undelegate; + } + + if (num_chans < req_chans) + dev_warn(&epf->dev, + "requested %u DMA channels, delegating %u\n", + req_chans, num_chans); + + dma =3D kzalloc_obj(*dma); + if (!dma) { + ret =3D -ENOMEM; + goto err_undelegate; + } + + dma_dev =3D epc->dev.parent; + align =3D epc_features->align ? epc_features->align : SZ_4K; + hdr_sz =3D ALIGN(sizeof(*hdr), align); + + dma->hdr_virt =3D dma_alloc_coherent(dma_dev, hdr_sz, &dma->hdr_phys, + GFP_KERNEL); + if (!dma->hdr_virt) { + ret =3D -ENOMEM; + goto err_free_dma; + } + + dma->epf =3D epf; + dma->bar =3D bar; + dma->hdr_alloc_size =3D hdr_sz; + dma->num_chans =3D num_chans; + dma->delegated_num_chans =3D delegated_chans; + memcpy(dma->delegated_chan_ids, chan_ids, + delegated_chans * sizeof(dma->delegated_chan_ids[0])); + + cur =3D offset; + dma->regions[dma->num_regions++] =3D (struct pci_ep_dma_region) { + .offset =3D cur, + .phys_addr =3D dma->hdr_phys, + .size =3D hdr_sz, + }; + cur +=3D hdr_sz; + + hdr =3D dma->hdr_virt; + memset(hdr, 0, sizeof(*hdr)); + hdr->magic =3D cpu_to_le32(PCI_EP_DMA_MAGIC); + hdr->version =3D cpu_to_le16(1); + hdr->hdr_size =3D cpu_to_le16(sizeof(*hdr)); + + /* + * If there is a fixed mapped DMA register block, reuse it. If the + * controller only reports a raw physical MMIO resource, map it into + * the exported slice so the peer still sees a self-contained BAR layout. + */ + if (ctrl->bar !=3D NO_BAR) { + hdr->ctrl_bar =3D cpu_to_le32(ctrl->bar); + hdr->ctrl_offset =3D cpu_to_le32(ctrl->bar_offset); + hdr->ctrl_size =3D cpu_to_le32(ctrl->size); + } else { + size_t map_sz; + u32 map_delta; + dma_addr_t map_addr; + + ret =3D pci_ep_dma_map_resource(dma_dev, ctrl->phys_addr, ctrl->size, + align, &map_addr, &map_sz, + &map_delta); + if (ret) + goto err_free_hdr; + + dma->ctrl_map_addr =3D map_addr; + dma->ctrl_map_size =3D map_sz; + dma->regions[dma->num_regions++] =3D (struct pci_ep_dma_region) { + .offset =3D cur, + .phys_addr =3D map_addr, + .size =3D map_sz, + }; + hdr->ctrl_bar =3D cpu_to_le32(bar); + hdr->ctrl_offset =3D cpu_to_le32(cur + map_delta); + hdr->ctrl_size =3D cpu_to_le32(ctrl->size); + cur +=3D map_sz; + } + + hdr->irq_count =3D cpu_to_le32(num_chans); + hdr->num_chans =3D cpu_to_le32(num_chans); + /* + * Preserve the delegated-channel order in @hdr->chans[]. ABI v1 currently + * assumes the exported READ channels form a dense prefix of the remote + * hardware READ-channel space, so dw-edma-aux consumes @chans[i] as remo= te + * READ channel i. + */ + for (i =3D 0; i < num_chans; i++) { + size_t desc_sz =3D ALIGN(descs[i]->size, align); + + dma->regions[dma->num_regions++] =3D (struct pci_ep_dma_region) { + .offset =3D cur, + .phys_addr =3D descs[i]->phys_addr, + .size =3D desc_sz, + }; + hdr->chans[i].desc_bar =3D cpu_to_le32(bar); + hdr->chans[i].desc_offset =3D cpu_to_le32(cur); + hdr->chans[i].desc_size =3D cpu_to_le32(descs[i]->size); + hdr->chans[i].desc_phys_addr =3D + cpu_to_le64(descs[i]->phys_addr); + cur +=3D desc_sz; + } + + hdr->total_size =3D cpu_to_le32(cur - offset); + dma->loc.abi =3D PCI_EP_DMA_ABI_V1; + dma->loc.bar =3D bar; + dma->loc.offset =3D offset; + dma->loc.size =3D cur - offset; + + kfree(res); + return dma; + +err_free_hdr: + if (dma->ctrl_map_addr) + dma_unmap_resource(dma_dev, dma->ctrl_map_addr, + dma->ctrl_map_size, + DMA_BIDIRECTIONAL, 0); + if (dma->hdr_virt) + dma_free_coherent(dma_dev, dma->hdr_alloc_size, + dma->hdr_virt, dma->hdr_phys); +err_free_dma: + kfree(dma); +err_undelegate: + { + int unret; + + unret =3D pci_ep_dma_undelegate_chans(epf, chan_ids, delegated_chans); + if (unret) + dev_warn(&epf->dev, + "failed to undelegate DMA channels: %d\n", + unret); + } +err_free_res: + kfree(res); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(pci_epf_alloc_dma); + +void pci_epf_free_dma(struct pci_ep_dma *dma) +{ + struct device *dma_dev; + int ret; + + if (!dma) + return; + + dma_dev =3D dma->epf->epc->dev.parent; + ret =3D pci_ep_dma_undelegate_chans(dma->epf, dma->delegated_chan_ids, + dma->delegated_num_chans); + if (ret) + dev_warn(&dma->epf->dev, + "failed to undelegate DMA channels: %d\n", ret); + if (dma->ctrl_map_addr) + dma_unmap_resource(dma_dev, dma->ctrl_map_addr, + dma->ctrl_map_size, + DMA_BIDIRECTIONAL, 0); + if (dma->hdr_virt) + dma_free_coherent(dma_dev, dma->hdr_alloc_size, + dma->hdr_virt, dma->hdr_phys); + kfree(dma); +} +EXPORT_SYMBOL_GPL(pci_epf_free_dma); + +const struct pci_ep_dma_locator *pci_epf_get_dma_locator(const struct pci_= ep_dma *dma) +{ + return dma ? &dma->loc : NULL; +} +EXPORT_SYMBOL_GPL(pci_epf_get_dma_locator); + +unsigned int pci_epf_get_dma_region_count(const struct pci_ep_dma *dma) +{ + return dma ? dma->num_regions : 0; +} +EXPORT_SYMBOL_GPL(pci_epf_get_dma_region_count); + +const struct pci_ep_dma_region *pci_epf_get_dma_regions(const struct pci_e= p_dma *dma) +{ + return dma ? dma->regions : NULL; +} +EXPORT_SYMBOL_GPL(pci_epf_get_dma_regions); diff --git a/include/linux/pci-ep-dma.h b/include/linux/pci-ep-dma.h new file mode 100644 index 000000000000..0ef6f9eb8593 --- /dev/null +++ b/include/linux/pci-ep-dma.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generic exported DMA helper for PCI endpoint functions + */ + +#ifndef __LINUX_PCI_EP_DMA_H +#define __LINUX_PCI_EP_DMA_H + +#include +#include + +#define PCI_EP_DMA_MAGIC 0x4d445045 /* "EPDM" */ +#define PCI_EP_DMA_MAX_CHANS 8 +#define PCI_EP_DMA_MAX_REGIONS (2 + PCI_EP_DMA_MAX_CHANS) + +enum pci_ep_dma_abi { + PCI_EP_DMA_ABI_NONE =3D 0, + PCI_EP_DMA_ABI_V1 =3D 1, +}; + +/** + * struct pci_ep_dma_locator - peer-visible location of an exported DMA sl= ice + * @abi: exported-DMA ABI identifier from &enum pci_ep_dma_abi + * @bar: BAR number that carries the exported slice + * @flags: ABI-specific locator flags, reserved for future use in v1 + * @offset: BAR-relative start offset of the exported slice + * @size: total size of the exported slice in bytes + */ +struct pci_ep_dma_locator { + u8 abi; + u8 bar; + u16 flags; + u32 offset; + u32 size; +}; + +/** + * struct pci_ep_dma_region - one physical region mapped into the exported= slice + * @offset: BAR-relative start offset of the region within the exported sl= ice + * @phys_addr: DMA address to program into the EPC BAR mapping + * @size: mapped size in bytes + */ +struct pci_ep_dma_region { + u32 offset; + dma_addr_t phys_addr; + size_t size; +}; + +/** + * struct pci_ep_dma_chan_info - per-channel descriptor metadata in ABI v1 + * @desc_bar: BAR number that exposes the descriptor window + * @desc_offset: BAR-relative start offset of the descriptor window + * @desc_size: descriptor window size in bytes + * @desc_phys_addr: physical/DMA address used for the EPC-side BAR mapping + */ +struct pci_ep_dma_chan_info { + __le32 desc_bar; + __le32 desc_offset; + __le32 desc_size; + __le64 desc_phys_addr; +}; + +/** + * struct pci_ep_dma_hdr_v1 - exported DMA header format, version 1 + * @magic: fixed signature, must be %PCI_EP_DMA_MAGIC + * @version: header version, must be 1 for this structure + * @hdr_size: size of the populated header structure in bytes + * @total_size: total exported-slice size starting at &struct pci_ep_dma_l= ocator.offset + * @ctrl_bar: BAR that exposes the live DMA control registers + * @ctrl_offset: BAR-relative start offset of the control-register window + * @ctrl_size: size of the control-register window in bytes + * @irq_count: number of IRQ vectors reserved for the exported DMA provider + * @num_chans: number of valid entries in @chans + * @chans: per-channel descriptor metadata + * + * Exported DMA ABI v1 lays out the peer-visible slice as: + * + * [header][controller window?][descriptor window 0]...[descriptor windo= w N] + * + * The controller window is optional in that slice. When the live register + * block is already exposed through another BAR, @ctrl_bar/@ctrl_offset po= int at + * that BAR directly and no controller subrange is embedded in the exported + * slice. + * + * @chans[] describes a dense prefix of the remote hardware READ-channel + * space, ordered by remote hardware READ-channel index starting at 0. A + * consumer may map @chans[i] directly to remote READ channel i. + */ +struct pci_ep_dma_hdr_v1 { + __le32 magic; + __le16 version; + __le16 hdr_size; + __le32 total_size; + __le32 ctrl_bar; + __le32 ctrl_offset; + __le32 ctrl_size; + __le32 irq_count; + __le32 num_chans; + struct pci_ep_dma_chan_info chans[PCI_EP_DMA_MAX_CHANS]; +}; + +struct pci_ep_dma { + struct pci_epf *epf; + enum pci_barno bar; + void *hdr_virt; + dma_addr_t hdr_phys; + size_t hdr_alloc_size; + struct pci_ep_dma_locator loc; + unsigned int num_regions; + u32 num_chans; + struct pci_ep_dma_region regions[PCI_EP_DMA_MAX_REGIONS]; + dma_addr_t ctrl_map_addr; + size_t ctrl_map_size; + int delegated_chan_ids[PCI_EP_DMA_MAX_CHANS]; + u8 delegated_num_chans; +}; + +struct pci_ep_dma *pci_epf_alloc_dma(struct pci_epf *epf, enum pci_barno b= ar, + u32 offset, u32 req_chans); +void pci_epf_free_dma(struct pci_ep_dma *dma); + +const struct pci_ep_dma_locator * +pci_epf_get_dma_locator(const struct pci_ep_dma *dma); + +unsigned int pci_epf_get_dma_region_count(const struct pci_ep_dma *dma); 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b=wyaqwR7i+yUgJAXjz7BC19kSq0+CEa9aUCH8vQr/mChAiK6GzNQdA+vX0Qpvbem2brpuQ0+pNSSyhS+Eq2NfkyF4GoYabjg5+8zyL0qnnQEFEtKLjpUqU1wtImax3Zym7cQLAUhs1AvKkUwv9iy9DUN6I/5aeowZrkG+731nX4A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=valinux.co.jp; Received: from TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) by TYCP286MB2018.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9700.15; Thu, 12 Mar 2026 16:50:19 +0000 Received: from TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM ([fe80::2305:327c:28ec:9b32]) by TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM ([fe80::2305:327c:28ec:9b32%5]) with mapi id 15.20.9700.013; Thu, 12 Mar 2026 16:50:19 +0000 From: Koichiro Den To: Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Shuah Khan , Vinod Koul , Frank Li , Jon Mason , Dave Jiang , Allen Hubbe , Jingoo Han , Lorenzo Pieralisi , Rob Herring , Baruch Siach , Jerome Brunet , Niklas Cassel Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, ntb@lists.linux.dev Subject: [PATCH 10/15] PCI: endpoint: pci-epf-vntb: Support DMA export and shared BAR layouts Date: Fri, 13 Mar 2026 01:50:00 +0900 Message-ID: <20260312165005.1148676-11-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260312165005.1148676-1-den@valinux.co.jp> References: <20260312165005.1148676-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0094.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b4::8) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB7722:EE_|TYCP286MB2018:EE_ X-MS-Office365-Filtering-Correlation-Id: 4101fcba-2cda-4593-6a7e-08de805771d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|10070799003|366016|7416014|921020|56012099003|22082099003|18002099003; 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charset="utf-8" Teach pci-epf-vntb to publish a versioned control layout and an optional exported DMA slice. When the configuration still matches the historical one-MW-per-BAR layout and DMA export is disabled, keep emitting the legacy control block. Otherwise emit control-layout v1, which adds per-MW offset/size tuples and a DMA locator for the exported slice. Add configfs knobs for mwN_offset, dma_bar, dma_offset, and dma_num_chans, and use pci_epf_alloc_dma() to prepare the DMA export. Also add BAR planning code so memory windows and the DMA slice can share a physical BAR. Shared layouts are programmed in two stages: install a temporary whole-BAR mapping at bind time, then switch to the final subrange map on the first host command once BAR addresses are valid. Signed-off-by: Koichiro Den --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 760 ++++++++++++++++-- 1 file changed, 707 insertions(+), 53 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 16656659a9ce..d493d64dca72 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -41,7 +41,9 @@ #include #include #include +#include =20 +#include #include #include #include @@ -69,6 +71,9 @@ static struct workqueue_struct *kpcintb_workqueue; #define MAX_DB_COUNT 32 #define MAX_MW 4 =20 +#define NTB_EPF_CTRL_VERSION_LEGACY 0 +#define NTB_EPF_CTRL_VERSION_V1 1 + /* Limit per-work execution to avoid monopolizing kworker on doorbell stor= ms. */ #define VNTB_PEER_DB_WORK_BUDGET 5 =20 @@ -79,6 +84,7 @@ enum epf_ntb_bar { BAR_MW2, BAR_MW3, BAR_MW4, + BAR_DMA, VNTB_BAR_NUM, }; =20 @@ -116,22 +122,41 @@ struct epf_ntb_ctrl { u32 argument; u16 command_status; u16 link_status; - u32 topology; + u32 ctrl_version; u64 addr; u64 size; u32 num_mws; - u32 reserved; + u32 mw1_offset; u32 spad_offset; u32 spad_count; u32 db_entry_size; u32 db_data[MAX_DB_COUNT]; u32 db_offset[MAX_DB_COUNT]; + u32 mw_offset[MAX_MW]; + u32 mw_size[MAX_MW]; + u32 dma_abi; + u32 dma_bar; + u32 dma_offset; + u32 dma_size; + u32 dma_num_chans; } __packed; =20 struct epf_ntb_mw { u64 size; + u32 offset; phys_addr_t vpci_mw_phys; void __iomem *vpci_mw_addr; + dma_addr_t bar_phys; +}; + +struct epf_ntb_bar_plan { + bool staged; + bool deferred; + bool active; + unsigned int region_count; + size_t size; + phys_addr_t stage_phys; + void __iomem *stage_addr; }; =20 struct epf_ntb { @@ -143,10 +168,14 @@ struct epf_ntb { u32 db_count; u32 spad_count; struct epf_ntb_mw mw[MAX_MW]; + struct epf_ntb_bar_plan bar_plan[PCI_STD_NUM_BARS]; atomic64_t db; atomic64_t peer_db_pending; struct work_struct peer_db_work; u32 vbus_number; + u32 dma_offset; + u32 dma_num_chans; + const struct pci_epc_features *epc_features; u16 vntb_pid; u16 vntb_vid; =20 @@ -162,6 +191,7 @@ struct epf_ntb { enum pci_barno epf_ntb_bar[VNTB_BAR_NUM]; =20 struct epf_ntb_ctrl *reg; + struct pci_ep_dma *dma; =20 u32 *epf_db; =20 @@ -260,6 +290,258 @@ static void epf_ntb_teardown_mw(struct epf_ntb *ntb, = u32 mw) ntb->mw[mw].vpci_mw_phys); } =20 +static bool epf_ntb_bar_valid(enum pci_barno barno) +{ + return barno >=3D BAR_0 && barno <=3D BAR_5; +} + +/* + * Legacy layout has no per-MW size array and no DMA locator. Only emit it + * when each MW owns a distinct BAR, all MWs after MW0 start at offset 0, + * and no DMA slice is exported, so older ntb_hw_epf can keep inferring + * the layout from BAR assignments alone. + */ +static bool epf_ntb_ctrl_layout_is_legacy(const struct epf_ntb *ntb) +{ + enum pci_barno barno; + u8 used_mw_bars =3D 0; + int i; + + if (ntb->dma) + return false; + + for (i =3D 0; i < ntb->num_mws; i++) { + barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; + if (epf_ntb_bar_valid(barno)) { + if (used_mw_bars & BIT(barno)) + return false; + used_mw_bars |=3D BIT(barno); + } + + if (i > 0 && ntb->mw[i].offset) + return false; + } + + return true; +} + +static int epf_ntb_validate_ctrl_layout_v1(const struct epf_ntb *ntb) +{ + struct device *dev =3D &ntb->epf->dev; + int i; + + if (epf_ntb_ctrl_layout_is_legacy(ntb)) + return 0; + + for (i =3D 0; i < ntb->num_mws; i++) { + if (ntb->mw[i].size > U32_MAX) { + dev_err(dev, + "MW%d size %#llx exceeds control ABI v1 limit\n", + i + 1, + (unsigned long long)ntb->mw[i].size); + return -E2BIG; + } + } + + return 0; +} + +static dma_addr_t epf_ntb_mw_active_phys(const struct epf_ntb *ntb, int id= x) +{ + if (ntb->mw[idx].bar_phys) + return ntb->mw[idx].bar_phys; + + return ntb->mw[idx].vpci_mw_phys; +} + +struct epf_ntb_bar_region { + u32 offset; + dma_addr_t phys_addr; + size_t size; +}; + +static int epf_ntb_bar_region_cmp(const void *a, const void *b) +{ + const struct epf_ntb_bar_region *ra =3D a; + const struct epf_ntb_bar_region *rb =3D b; + + if (ra->offset < rb->offset) + return -1; + + return ra->offset > rb->offset; +} + +static int +epf_ntb_add_bar_region(struct epf_ntb_bar_region *regions, + unsigned int *count, u32 offset, dma_addr_t phys_addr, + size_t size, bool needs_phys_addr) +{ + if (needs_phys_addr && !phys_addr) + return -EINVAL; + + regions[*count] =3D (struct epf_ntb_bar_region) { + .offset =3D offset, + .phys_addr =3D phys_addr, + .size =3D size, + }; + (*count)++; + + return 0; +} + +static int +epf_ntb_collect_bar_regions(struct epf_ntb *ntb, enum pci_barno barno, + struct pci_epf_bar_submap *submap, + unsigned int *nregions, size_t *total) +{ + struct epf_ntb_bar_region regions[MAX_MW + PCI_EP_DMA_MAX_REGIONS]; + const struct pci_ep_dma_region *dma_regions; + struct device *dev =3D &ntb->epf->dev; + bool needs_phys_addr =3D !!submap; + unsigned int count =3D 0; + size_t size_total =3D 0; + int i, ret; + + if (ntb->dma && ntb->epf_ntb_bar[BAR_DMA] =3D=3D barno) { + dma_regions =3D pci_epf_get_dma_regions(ntb->dma); + for (i =3D 0; i < pci_epf_get_dma_region_count(ntb->dma); i++) { + ret =3D epf_ntb_add_bar_region(regions, &count, + dma_regions[i].offset, + dma_regions[i].phys_addr, + dma_regions[i].size, + needs_phys_addr); + if (ret) + return ret; + } + } + + for (i =3D 0; i < ntb->num_mws; i++) { + if (ntb->epf_ntb_bar[BAR_MW1 + i] !=3D barno) + continue; + + ret =3D epf_ntb_add_bar_region(regions, &count, ntb->mw[i].offset, + needs_phys_addr ? + epf_ntb_mw_active_phys(ntb, i) : 0, + ntb->mw[i].size, needs_phys_addr); + if (ret) + return ret; + } + + if (!count) + return -EINVAL; + + sort(regions, count, sizeof(regions[0]), epf_ntb_bar_region_cmp, NULL); + + for (i =3D 0; i < count; i++) { + if (!regions[i].size || regions[i].offset !=3D size_total) + return -EINVAL; + if (submap) { + submap[i].phys_addr =3D regions[i].phys_addr; + submap[i].size =3D regions[i].size; + } + size_total +=3D regions[i].size; + } + + if (!is_power_of_2(size_total)) { + dev_err(dev, "Invalid total size: %#lx\n", size_total); + return -EINVAL; + } + + *nregions =3D count; + *total =3D size_total; + + return 0; +} + +static int epf_ntb_bar_activate(struct epf_ntb *ntb, enum pci_barno barno) +{ + struct epf_ntb_bar_plan *plan =3D &ntb->bar_plan[barno]; + struct pci_epf_bar_submap *submap =3D NULL, *old_submap; + struct pci_epf_bar *epf_bar =3D &ntb->epf->bar[barno]; + unsigned int nregions, old_nsub; + phys_addr_t old_phys; + size_t total; + int ret; + + if (!plan->staged || !plan->deferred) + return 0; + + submap =3D kcalloc(plan->region_count, sizeof(*submap), GFP_KERNEL); + if (!submap) + return -ENOMEM; + + ret =3D epf_ntb_collect_bar_regions(ntb, barno, submap, &nregions, &total= ); + if (ret) + goto err_free; + if (nregions !=3D plan->region_count || total !=3D plan->size) { + ret =3D -EINVAL; + goto err_free; + } + + old_phys =3D epf_bar->phys_addr; + old_submap =3D epf_bar->submap; + old_nsub =3D epf_bar->num_submap; + + epf_bar->phys_addr =3D 0; + epf_bar->submap =3D submap; + epf_bar->num_submap =3D nregions; + epf_bar->size =3D total; + + ret =3D pci_epc_set_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + epf_bar); + if (ret) { + epf_bar->phys_addr =3D old_phys; + epf_bar->submap =3D old_submap; + epf_bar->num_submap =3D old_nsub; + goto err_free; + } + + if (plan->stage_addr) { + pci_epc_mem_free_addr(ntb->epf->epc, plan->stage_phys, + plan->stage_addr, plan->size); + plan->stage_addr =3D NULL; + plan->stage_phys =3D 0; + } + kfree(old_submap); + plan->active =3D true; + return 0; + +err_free: + kfree(submap); + return ret; +} + +static int epf_ntb_bar_activate_deferred(struct epf_ntb *ntb) +{ + bool done[PCI_STD_NUM_BARS] =3D { }; + enum pci_barno barno; + int i, ret; + + for (i =3D 0; i < ntb->num_mws; i++) { + barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; + if (!epf_ntb_bar_valid(barno) || done[barno]) + continue; + if (!ntb->bar_plan[barno].active) { + ret =3D epf_ntb_bar_activate(ntb, barno); + if (ret) + return ret; + } + done[barno] =3D true; + } + + barno =3D ntb->epf_ntb_bar[BAR_DMA]; + if (epf_ntb_bar_valid(barno) && !done[barno] && + !ntb->bar_plan[barno].active) { + ret =3D epf_ntb_bar_activate(ntb, barno); + if (ret) + return ret; + } + + return 0; +} + /** * epf_ntb_cmd_handler() - Handle commands provided by the NTB HOST * @work: work_struct for the epf_ntb_epc @@ -309,6 +591,11 @@ static void epf_ntb_cmd_handler(struct work_struct *wo= rk) ctrl->command_status =3D COMMAND_STATUS_OK; break; case COMMAND_CONFIGURE_MW: + ret =3D epf_ntb_bar_activate_deferred(ntb); + if (ret < 0) { + ctrl->command_status =3D COMMAND_STATUS_ERROR; + break; + } ret =3D epf_ntb_configure_mw(ntb, argument); if (ret < 0) ctrl->command_status =3D COMMAND_STATUS_ERROR; @@ -320,6 +607,11 @@ static void epf_ntb_cmd_handler(struct work_struct *wo= rk) ctrl->command_status =3D COMMAND_STATUS_OK; break; case COMMAND_LINK_UP: + ret =3D epf_ntb_bar_activate_deferred(ntb); + if (ret < 0) { + ctrl->command_status =3D COMMAND_STATUS_ERROR; + goto reset_handler; + } ntb->linkup =3D true; ret =3D epf_ntb_link_up(ntb, true); if (ret < 0) @@ -476,8 +768,35 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_nt= b *ntb) ctrl =3D ntb->reg; ctrl->spad_offset =3D ctrl_size; =20 + ctrl->ctrl_version =3D epf_ntb_ctrl_layout_is_legacy(ntb) ? + NTB_EPF_CTRL_VERSION_LEGACY : NTB_EPF_CTRL_VERSION_V1; ctrl->spad_count =3D spad_count; ctrl->num_mws =3D ntb->num_mws; + ctrl->mw1_offset =3D ntb->num_mws ? ntb->mw[0].offset : 0; + + if (ctrl->ctrl_version >=3D NTB_EPF_CTRL_VERSION_V1) { + for (i =3D 0; i < ntb->num_mws; i++) { + ctrl->mw_offset[i] =3D ntb->mw[i].offset; + ctrl->mw_size[i] =3D ntb->mw[i].size; + } + + if (ntb->dma) { + const struct pci_ep_dma_locator *loc =3D + pci_epf_get_dma_locator(ntb->dma); + + ctrl->dma_abi =3D loc->abi; + ctrl->dma_bar =3D loc->bar; + ctrl->dma_offset =3D loc->offset; + ctrl->dma_size =3D loc->size; + ctrl->dma_num_chans =3D ntb->dma->num_chans; + } else { + ctrl->dma_abi =3D 0; + ctrl->dma_bar =3D NO_BAR; + ctrl->dma_offset =3D 0; + ctrl->dma_size =3D 0; + ctrl->dma_num_chans =3D 0; + } + } ntb->spad_size =3D spad_size; =20 ctrl->db_entry_size =3D sizeof(u32); @@ -509,6 +828,7 @@ static int epf_ntb_configure_interrupt(struct epf_ntb *= ntb) dev =3D &ntb->epf->dev; =20 epc_features =3D pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, n= tb->epf->vfunc_no); + ntb->epc_features =3D epc_features; =20 if (!(epc_features->msix_capable || epc_features->msi_capable)) { dev_err(dev, "MSI or MSI-X is required for doorbell\n"); @@ -721,6 +1041,35 @@ static int epf_ntb_db_bar_init(struct epf_ntb *ntb) =20 static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws); =20 +static void epf_ntb_dma_cleanup(struct epf_ntb *ntb) +{ + if (!ntb->dma) + return; + + pci_epf_free_dma(ntb->dma); + ntb->dma =3D NULL; +} + +static int epf_ntb_dma_prepare(struct epf_ntb *ntb) +{ + enum pci_barno barno; + + barno =3D ntb->epf_ntb_bar[BAR_DMA]; + if (barno =3D=3D NO_BAR) + return 0; + + ntb->dma =3D pci_epf_alloc_dma(ntb->epf, barno, ntb->dma_offset, + ntb->dma_num_chans ?: 1); + if (IS_ERR(ntb->dma)) { + int ret =3D PTR_ERR(ntb->dma); + + ntb->dma =3D NULL; + return ret; + } + + return 0; +} + /** * epf_ntb_db_bar_clear() - Clear doorbell BAR and free memory * allocated in peer's outbound address space @@ -751,6 +1100,169 @@ static void epf_ntb_db_bar_clear(struct epf_ntb *ntb) &ntb->epf->bar[barno]); } =20 +static int +epf_ntb_validate_one_bar_layout(struct epf_ntb *ntb, enum pci_barno barno) +{ + unsigned int count; + size_t total; + int ret; + + ret =3D epf_ntb_collect_bar_regions(ntb, barno, NULL, &count, &total); + if (ret) + return ret; + + if (count <=3D 1 || + (ntb->epc_features->subrange_mapping && + ntb->epc_features->dynamic_inbound_mapping)) + return 0; + + dev_err(&ntb->epf->dev, + "BAR%d requires %u regions but subrange mapping unsupported\n", + barno, count); + + return -EOPNOTSUPP; +} + +static int epf_ntb_validate_bar_layout(struct epf_ntb *ntb) +{ + bool checked[PCI_STD_NUM_BARS] =3D { }; + enum pci_barno barno; + int i, ret; + + for (i =3D 0; i < ntb->num_mws; i++) { + barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; + if (!epf_ntb_bar_valid(barno) || checked[barno]) + continue; + + ret =3D epf_ntb_validate_one_bar_layout(ntb, barno); + if (ret) + return ret; + + checked[barno] =3D true; + } + + barno =3D ntb->epf_ntb_bar[BAR_DMA]; + if (!epf_ntb_bar_valid(barno) || checked[barno]) + return 0; + + return epf_ntb_validate_one_bar_layout(ntb, barno); +} + +/* + * Shared MW/DMA BARs are programmed in two stages. At bind time the host + * has not assigned BAR addresses yet, so install a temporary whole-BAR + * mapping first. Once the first host command arrives and BAR addresses + * are valid, replace it with the final subrange layout. + */ +static int epf_ntb_bar_stage1_program(struct epf_ntb *ntb, enum pci_barno = barno) +{ + struct pci_epf_bar_submap regions[MAX_MW + PCI_EP_DMA_MAX_REGIONS]; + struct epf_ntb_bar_plan *plan =3D &ntb->bar_plan[barno]; + struct pci_epf_bar *epf_bar =3D &ntb->epf->bar[barno]; + unsigned int nregions; + size_t total; + int ret; + + ret =3D epf_ntb_collect_bar_regions(ntb, barno, regions, &nregions, &tota= l); + if (ret) + return ret; + + plan->region_count =3D nregions; + plan->size =3D total; + plan->deferred =3D nregions > 1; + plan->active =3D !plan->deferred; + + if (plan->deferred) { + plan->stage_addr =3D pci_epc_mem_alloc_addr(ntb->epf->epc, + &plan->stage_phys, + total); + if (!plan->stage_addr) + return -ENOMEM; + } + + epf_bar->barno =3D barno; + epf_bar->size =3D total; + epf_bar->addr =3D NULL; + epf_bar->flags =3D upper_32_bits(total) ? + PCI_BASE_ADDRESS_MEM_TYPE_64 : PCI_BASE_ADDRESS_MEM_TYPE_32; + epf_bar->submap =3D NULL; + epf_bar->num_submap =3D 0; + epf_bar->phys_addr =3D plan->deferred ? plan->stage_phys : regions[0].phy= s_addr; + + ret =3D pci_epc_set_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + epf_bar); + if (ret) { + if (plan->stage_addr) { + pci_epc_mem_free_addr(ntb->epf->epc, plan->stage_phys, + plan->stage_addr, total); + plan->stage_addr =3D NULL; + plan->stage_phys =3D 0; + } + return ret; + } + + plan->staged =3D true; + return 0; +} + +static int epf_ntb_bar_refresh(struct epf_ntb *ntb, enum pci_barno barno) +{ + struct epf_ntb_bar_plan *plan =3D &ntb->bar_plan[barno]; + struct pci_epf_bar *epf_bar =3D &ntb->epf->bar[barno]; + struct pci_epf_bar_submap region; + unsigned int nregions; + size_t total; + int ret; + + if (!plan->staged) + return 0; + + if (plan->deferred) + return plan->active ? epf_ntb_bar_activate(ntb, barno) : 0; + + ret =3D epf_ntb_collect_bar_regions(ntb, barno, ®ion, &nregions, &tota= l); + if (ret) + return ret; + if (nregions !=3D 1 || total !=3D plan->size) + return -EINVAL; + + epf_bar->phys_addr =3D region.phys_addr; + epf_bar->submap =3D NULL; + epf_bar->num_submap =3D 0; + epf_bar->size =3D total; + + return pci_epc_set_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + epf_bar); +} + +static void epf_ntb_mw_bar_release(struct epf_ntb *ntb, enum pci_barno bar= no) +{ + struct epf_ntb_bar_plan *plan =3D &ntb->bar_plan[barno]; + struct pci_epf_bar *epf_bar =3D &ntb->epf->bar[barno]; + + if (!plan->staged) + return; + + pci_epc_clear_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + epf_bar); + kfree(epf_bar->submap); + epf_bar->submap =3D NULL; + epf_bar->num_submap =3D 0; + if (plan->stage_addr) { + pci_epc_mem_free_addr(ntb->epf->epc, plan->stage_phys, + plan->stage_addr, plan->size); + plan->stage_addr =3D NULL; + plan->stage_phys =3D 0; + } + memset(plan, 0, sizeof(*plan)); +} + /** * epf_ntb_mw_bar_init() - Configure Memory window BARs * @ntb: NTB device that facilitates communication between HOST and VHOST @@ -759,54 +1271,55 @@ static void epf_ntb_db_bar_clear(struct epf_ntb *ntb) */ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) { + bool programmed[PCI_STD_NUM_BARS] =3D { }; + struct device *dev =3D &ntb->epf->dev; + enum pci_barno barno; int ret =3D 0; int i; - u64 size; - enum pci_barno barno; - struct device *dev =3D &ntb->epf->dev; =20 for (i =3D 0; i < ntb->num_mws; i++) { - size =3D ntb->mw[i].size; - barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; + if (!ntb->mw[i].size) + return -EINVAL; =20 - ntb->epf->bar[barno].barno =3D barno; - ntb->epf->bar[barno].size =3D size; - ntb->epf->bar[barno].addr =3D NULL; - ntb->epf->bar[barno].phys_addr =3D 0; - ntb->epf->bar[barno].flags |=3D upper_32_bits(size) ? - PCI_BASE_ADDRESS_MEM_TYPE_64 : - PCI_BASE_ADDRESS_MEM_TYPE_32; - - ret =3D pci_epc_set_bar(ntb->epf->epc, - ntb->epf->func_no, - ntb->epf->vfunc_no, - &ntb->epf->bar[barno]); - if (ret) { - dev_err(dev, "MW set failed\n"); - goto err_alloc_mem; - } - - /* Allocate EPC outbound memory windows to vpci vntb device */ ntb->mw[i].vpci_mw_addr =3D pci_epc_mem_alloc_addr(ntb->epf->epc, &ntb->mw[i].vpci_mw_phys, - size); + ntb->mw[i].size); if (!ntb->mw[i].vpci_mw_addr) { ret =3D -ENOMEM; dev_err(dev, "Failed to allocate source address\n"); - goto err_set_bar; + goto err_alloc; + } + + barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; + if (!epf_ntb_bar_valid(barno)) { + ret =3D -EINVAL; + goto err_alloc; + } + if (programmed[barno]) + continue; + + ret =3D epf_ntb_bar_stage1_program(ntb, barno); + if (ret) { + dev_err(dev, "MW BAR stage1 set failed\n"); + goto err_alloc; } + programmed[barno] =3D true; } =20 - return ret; + barno =3D ntb->epf_ntb_bar[BAR_DMA]; + if (ntb->dma && epf_ntb_bar_valid(barno) && !programmed[barno]) { + ret =3D epf_ntb_bar_stage1_program(ntb, barno); + if (ret) { + dev_err(dev, "DMA BAR stage1 set failed\n"); + goto err_alloc; + } + } =20 -err_set_bar: - pci_epc_clear_bar(ntb->epf->epc, - ntb->epf->func_no, - ntb->epf->vfunc_no, - &ntb->epf->bar[barno]); -err_alloc_mem: - epf_ntb_mw_bar_clear(ntb, i); + return 0; + +err_alloc: + epf_ntb_mw_bar_clear(ntb, ntb->num_mws); return ret; } =20 @@ -817,21 +1330,32 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) */ static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws) { + bool cleared[PCI_STD_NUM_BARS] =3D { }; enum pci_barno barno; int i; =20 for (i =3D 0; i < num_mws; i++) { barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; - pci_epc_clear_bar(ntb->epf->epc, - ntb->epf->func_no, - ntb->epf->vfunc_no, - &ntb->epf->bar[barno]); + if (epf_ntb_bar_valid(barno) && !cleared[barno]) { + epf_ntb_mw_bar_release(ntb, barno); + cleared[barno] =3D true; + } + + if (!ntb->mw[i].vpci_mw_addr) + continue; =20 pci_epc_mem_free_addr(ntb->epf->epc, ntb->mw[i].vpci_mw_phys, ntb->mw[i].vpci_mw_addr, ntb->mw[i].size); + ntb->mw[i].vpci_mw_addr =3D NULL; + ntb->mw[i].vpci_mw_phys =3D 0; + ntb->mw[i].bar_phys =3D 0; } + + barno =3D ntb->epf_ntb_bar[BAR_DMA]; + if (ntb->dma && epf_ntb_bar_valid(barno) && !cleared[barno]) + epf_ntb_mw_bar_release(ntb, barno); } =20 /** @@ -910,6 +1434,11 @@ static int epf_ntb_init_epc_bar(struct epf_ntb *ntb) num_mws =3D ntb->num_mws; dev =3D &ntb->epf->dev; epc_features =3D pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, n= tb->epf->vfunc_no); + if (!epc_features) { + dev_err(dev, "Failed to get EPC features\n"); + return -ENODEV; + } + ntb->epc_features =3D epc_features; =20 /* These are required BARs which are mandatory for NTB functionality */ for (bar =3D BAR_CONFIG; bar <=3D BAR_MW1; bar++) { @@ -1102,6 +1631,59 @@ static ssize_t epf_ntb_##_name##_store(struct config= _item *item, \ return len; \ } =20 +#define EPF_NTB_MW_OFF_R(_name) \ +static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct config_group *group =3D to_config_group(item); \ + struct epf_ntb *ntb =3D to_epf_ntb(group); \ + struct device *dev =3D &ntb->epf->dev; \ + int win_no, idx; \ + \ + if (sscanf(#_name, "mw%d_offset", &win_no) !=3D 1) \ + return -EINVAL; \ + \ + idx =3D win_no - 1; \ + if (idx < 0 || idx >=3D ntb->num_mws) { \ + dev_err(dev, "MW%d out of range (num_mws=3D%d)\n", \ + win_no, ntb->num_mws); \ + return -ERANGE; \ + } \ + idx =3D array_index_nospec(idx, ntb->num_mws); \ + \ + return sprintf(page, "%u\n", ntb->mw[idx].offset); \ +} + +#define EPF_NTB_MW_OFF_W(_name) \ +static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct config_group *group =3D to_config_group(item); \ + struct epf_ntb *ntb =3D to_epf_ntb(group); \ + struct device *dev =3D &ntb->epf->dev; \ + int win_no, idx; \ + u32 val; \ + int ret; \ + \ + ret =3D kstrtou32(page, 0, &val); \ + if (ret) \ + return ret; \ + \ + if (sscanf(#_name, "mw%d_offset", &win_no) !=3D 1) \ + return -EINVAL; \ + \ + idx =3D win_no - 1; \ + if (idx < 0 || idx >=3D ntb->num_mws) { \ + dev_err(dev, "MW%d out of range (num_mws=3D%d)\n", \ + win_no, ntb->num_mws); \ + return -ERANGE; \ + } \ + idx =3D array_index_nospec(idx, ntb->num_mws); \ + ntb->mw[idx].offset =3D val; \ + \ + return len; \ +} + #define EPF_NTB_BAR_R(_name, _id) \ static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ char *page) \ @@ -1153,6 +1735,30 @@ static ssize_t epf_ntb_num_mws_store(struct config_i= tem *item, return len; } =20 +static ssize_t epf_ntb_dma_offset_show(struct config_item *item, char *pag= e) +{ + struct config_group *group =3D to_config_group(item); + struct epf_ntb *ntb =3D to_epf_ntb(group); + + return sprintf(page, "%u\n", ntb->dma_offset); +} + +static ssize_t epf_ntb_dma_offset_store(struct config_item *item, + const char *page, size_t len) +{ + struct config_group *group =3D to_config_group(item); + struct epf_ntb *ntb =3D to_epf_ntb(group); + u32 val; + int ret; + + ret =3D kstrtou32(page, 0, &val); + if (ret) + return ret; + + ntb->dma_offset =3D val; + return len; +} + EPF_NTB_R(spad_count) EPF_NTB_W(spad_count) EPF_NTB_R(db_count) @@ -1164,6 +1770,8 @@ EPF_NTB_R(vntb_pid) EPF_NTB_W(vntb_pid) EPF_NTB_R(vntb_vid) EPF_NTB_W(vntb_vid) +EPF_NTB_R(dma_num_chans) +EPF_NTB_W(dma_num_chans) EPF_NTB_MW_R(mw1) EPF_NTB_MW_W(mw1) EPF_NTB_MW_R(mw2) @@ -1172,6 +1780,14 @@ EPF_NTB_MW_R(mw3) EPF_NTB_MW_W(mw3) EPF_NTB_MW_R(mw4) EPF_NTB_MW_W(mw4) +EPF_NTB_MW_OFF_R(mw1_offset) +EPF_NTB_MW_OFF_W(mw1_offset) +EPF_NTB_MW_OFF_R(mw2_offset) +EPF_NTB_MW_OFF_W(mw2_offset) +EPF_NTB_MW_OFF_R(mw3_offset) +EPF_NTB_MW_OFF_W(mw3_offset) +EPF_NTB_MW_OFF_R(mw4_offset) +EPF_NTB_MW_OFF_W(mw4_offset) EPF_NTB_BAR_R(ctrl_bar, BAR_CONFIG) EPF_NTB_BAR_W(ctrl_bar, BAR_CONFIG) EPF_NTB_BAR_R(db_bar, BAR_DB) @@ -1184,6 +1800,8 @@ EPF_NTB_BAR_R(mw3_bar, BAR_MW3) EPF_NTB_BAR_W(mw3_bar, BAR_MW3) EPF_NTB_BAR_R(mw4_bar, BAR_MW4) EPF_NTB_BAR_W(mw4_bar, BAR_MW4) +EPF_NTB_BAR_R(dma_bar, BAR_DMA) +EPF_NTB_BAR_W(dma_bar, BAR_DMA) =20 CONFIGFS_ATTR(epf_ntb_, spad_count); CONFIGFS_ATTR(epf_ntb_, db_count); @@ -1192,15 +1810,22 @@ CONFIGFS_ATTR(epf_ntb_, mw1); CONFIGFS_ATTR(epf_ntb_, mw2); CONFIGFS_ATTR(epf_ntb_, mw3); CONFIGFS_ATTR(epf_ntb_, mw4); +CONFIGFS_ATTR(epf_ntb_, mw1_offset); +CONFIGFS_ATTR(epf_ntb_, mw2_offset); +CONFIGFS_ATTR(epf_ntb_, mw3_offset); +CONFIGFS_ATTR(epf_ntb_, mw4_offset); CONFIGFS_ATTR(epf_ntb_, vbus_number); CONFIGFS_ATTR(epf_ntb_, vntb_pid); CONFIGFS_ATTR(epf_ntb_, vntb_vid); +CONFIGFS_ATTR(epf_ntb_, dma_num_chans); CONFIGFS_ATTR(epf_ntb_, ctrl_bar); CONFIGFS_ATTR(epf_ntb_, db_bar); CONFIGFS_ATTR(epf_ntb_, mw1_bar); CONFIGFS_ATTR(epf_ntb_, mw2_bar); CONFIGFS_ATTR(epf_ntb_, mw3_bar); CONFIGFS_ATTR(epf_ntb_, mw4_bar); +CONFIGFS_ATTR(epf_ntb_, dma_bar); +CONFIGFS_ATTR(epf_ntb_, dma_offset); =20 static struct configfs_attribute *epf_ntb_attrs[] =3D { &epf_ntb_attr_spad_count, @@ -1210,15 +1835,22 @@ static struct configfs_attribute *epf_ntb_attrs[] = =3D { &epf_ntb_attr_mw2, &epf_ntb_attr_mw3, &epf_ntb_attr_mw4, + &epf_ntb_attr_mw1_offset, + &epf_ntb_attr_mw2_offset, + &epf_ntb_attr_mw3_offset, + &epf_ntb_attr_mw4_offset, &epf_ntb_attr_vbus_number, &epf_ntb_attr_vntb_pid, &epf_ntb_attr_vntb_vid, + &epf_ntb_attr_dma_num_chans, &epf_ntb_attr_ctrl_bar, &epf_ntb_attr_db_bar, &epf_ntb_attr_mw1_bar, &epf_ntb_attr_mw2_bar, &epf_ntb_attr_mw3_bar, &epf_ntb_attr_mw4_bar, + &epf_ntb_attr_dma_bar, + &epf_ntb_attr_dma_offset, NULL, }; =20 @@ -1372,29 +2004,33 @@ static int vntb_epf_mw_set_trans(struct ntb_dev *nd= ev, int pidx, int idx, dma_addr_t addr, resource_size_t size) { struct epf_ntb *ntb =3D ntb_ndev(ndev); - struct pci_epf_bar *epf_bar; + struct device *dev =3D &ntb->ntb.dev; enum pci_barno barno; int ret; - struct device *dev; =20 - dev =3D &ntb->ntb.dev; barno =3D ntb->epf_ntb_bar[BAR_MW1 + idx]; - epf_bar =3D &ntb->epf->bar[barno]; - epf_bar->phys_addr =3D addr; - epf_bar->barno =3D barno; - epf_bar->size =3D size; + if (size !=3D ntb->mw[idx].size) { + dev_err(dev, "unsupported MW resize for shared BAR layout\n"); + return -EINVAL; + } =20 - ret =3D pci_epc_set_bar(ntb->epf->epc, 0, 0, epf_bar); - if (ret) { + ntb->mw[idx].bar_phys =3D addr; + ret =3D epf_ntb_bar_refresh(ntb, barno); + if (ret) dev_err(dev, "failure set mw trans\n"); - return ret; - } - return 0; + + return ret; } =20 -static int vntb_epf_mw_clear_trans(struct ntb_dev *ntb, int pidx, int idx) +static int vntb_epf_mw_clear_trans(struct ntb_dev *ndev, int pidx, int idx) { - return 0; + struct epf_ntb *ntb =3D ntb_ndev(ndev); + enum pci_barno barno; + + barno =3D ntb->epf_ntb_bar[BAR_MW1 + idx]; + + ntb->mw[idx].bar_phys =3D 0; + return epf_ntb_bar_refresh(ntb, barno); } =20 static int vntb_epf_peer_mw_get_addr(struct ntb_dev *ndev, int idx, @@ -1695,6 +2331,22 @@ static int epf_ntb_bind(struct pci_epf *epf) return ret; } =20 + ret =3D epf_ntb_dma_prepare(ntb); + if (ret) { + dev_err(dev, "Failed to prepare DMA export\n"); + goto err_bar_alloc; + } + + ret =3D epf_ntb_validate_bar_layout(ntb); + if (ret) { + dev_err(dev, "Unsupported BAR layout for this EPC\n"); + goto err_bar_alloc; + } + + ret =3D epf_ntb_validate_ctrl_layout_v1(ntb); + if (ret) + goto err_bar_alloc; + ret =3D epf_ntb_config_spad_bar_alloc(ntb); if (ret) { dev_err(dev, "Failed to allocate BAR memory\n"); @@ -1730,6 +2382,7 @@ static int epf_ntb_bind(struct pci_epf *epf) err_epc_cleanup: epf_ntb_epc_cleanup(ntb); err_bar_alloc: + epf_ntb_dma_cleanup(ntb); epf_ntb_config_spad_bar_free(ntb); =20 return ret; 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Thu, 12 Mar 2026 16:50:20 +0000 From: Koichiro Den To: Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Shuah Khan , Vinod Koul , Frank Li , Jon Mason , Dave Jiang , Allen Hubbe , Jingoo Han , Lorenzo Pieralisi , Rob Herring , Baruch Siach , Jerome Brunet , Niklas Cassel Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, ntb@lists.linux.dev Subject: [PATCH 11/15] NTB: hw: epf: Parse control-layout version and DMA locator Date: Fri, 13 Mar 2026 01:50:01 +0900 Message-ID: <20260312165005.1148676-12-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260312165005.1148676-1-den@valinux.co.jp> References: <20260312165005.1148676-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0092.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b4::10) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB7722:EE_|TYCP286MB2018:EE_ X-MS-Office365-Filtering-Correlation-Id: e320442e-fdab-410f-d358-08de80577245 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|10070799003|366016|7416014|921020|56012099003|22082099003|18002099003; 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charset="utf-8" pci-epf-vntb can now expose either the historical control layout or a versioned extension that carries per-MW offset/size tuples and an optional DMA locator. Teach ntb_hw_epf to parse the control-layout version first, keep accepting the legacy format, and use the explicit MW size information when version 1 is present. Also parse the DMA locator and cache its BAR, offset, size, ABI, and channel count for the follow-up enumeration step. Finally, reserve the tail of the MSI/MSI-X vector allocation for the exported DMA child so ntb_hw_epf only requests the link and doorbell vectors it owns. Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/ntb_hw_epf.c | 112 +++++++++++++++++++++++++++++--- 1 file changed, 104 insertions(+), 8 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index d420699ff7d6..6b427577b1bd 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -31,7 +31,14 @@ #define NTB_EPF_LINK_STATUS 0x0A #define LINK_STATUS_UP BIT(0) =20 -#define NTB_EPF_TOPOLOGY 0x0C +/* + * 0x0C was historically NTB_EPF_TOPOLOGY, but neither ntb_hw_epf nor + * pci-epf-{v,}ntb ever consumed it. Reuse it as a control-layout version + * selector while keeping 0 as the legacy format. + */ +#define NTB_EPF_CTRL_VERSION 0x0C +#define NTB_EPF_CTRL_VERSION_LEGACY 0 +#define NTB_EPF_CTRL_VERSION_V1 1 #define NTB_EPF_LOWER_ADDR 0x10 #define NTB_EPF_UPPER_ADDR 0x14 #define NTB_EPF_LOWER_SIZE 0x18 @@ -39,6 +46,13 @@ #define NTB_EPF_MW_COUNT 0x20 #define NTB_EPF_MW1_OFFSET 0x24 #define NTB_EPF_SPAD_OFFSET 0x28 +#define NTB_EPF_MW_OFFSET(n) (0x134 + (n) * 4) +#define NTB_EPF_MW_SIZE(n) (0x144 + (n) * 4) +#define NTB_EPF_DMA_ABI 0x154 +#define NTB_EPF_DMA_BAR 0x158 +#define NTB_EPF_DMA_OFFSET 0x15C +#define NTB_EPF_DMA_SIZE 0x160 +#define NTB_EPF_DMA_NUM_CHANS 0x164 #define NTB_EPF_SPAD_COUNT 0x2C #define NTB_EPF_DB_ENTRY_SIZE 0x30 #define NTB_EPF_DB_DATA(n) (0x34 + (n) * 4) @@ -101,6 +115,15 @@ struct ntb_epf_dev { unsigned int mw_count; unsigned int spad_count; unsigned int db_count; + u32 ctrl_version; + u32 dma_abi; + u32 dma_offset; + u32 dma_size; + u32 dma_num_chans; + u32 dma_irq_base; + u32 dma_irq_count; + enum pci_barno dma_bar; + bool dma_aux_avail; =20 void __iomem *ctrl_reg; void __iomem *db_reg; @@ -375,6 +398,21 @@ static int ntb_epf_init_isr(struct ntb_epf_dev *ndev, = int msi_min, int msi_max) argument &=3D ~MSIX_ENABLE; } =20 + if (irq >=3D msi_min + ndev->dma_irq_count) { + ndev->dma_aux_avail =3D true; + + /* + * Reserve the tail of the vector space for the exported DMA + * child. ntb_hw_epf only requests the prefix used for link and + * doorbell events. + */ + ndev->dma_irq_base =3D irq - ndev->dma_irq_count; + irq =3D ndev->dma_irq_base; + } else { + ndev->dma_aux_avail =3D false; + irq =3D min(NTB_EPF_MAX_DB_COUNT + 1, irq); + } + for (i =3D 0; i < irq; i++) { ret =3D request_irq(pci_irq_vector(pdev, i), ntb_epf_vec_isr, 0, "ntb_epf", ndev); @@ -504,21 +542,32 @@ static int ntb_epf_peer_mw_get_addr(struct ntb_dev *n= tb, int idx, phys_addr_t *base, resource_size_t *size) { struct ntb_epf_dev *ndev =3D ntb_ndev(ntb); - u32 offset =3D 0; + resource_size_t bar_sz, mw_size; + u32 offset; int bar; =20 - if (idx =3D=3D 0) - offset =3D readl(ndev->ctrl_reg + NTB_EPF_MW1_OFFSET); - bar =3D ntb_epf_mw_to_bar(ndev, idx); if (bar < 0) return bar; =20 + bar_sz =3D pci_resource_len(ndev->ntb.pdev, bar); + + if (ndev->ctrl_version >=3D NTB_EPF_CTRL_VERSION_V1) { + offset =3D readl(ndev->ctrl_reg + NTB_EPF_MW_OFFSET(idx)); + mw_size =3D readl(ndev->ctrl_reg + NTB_EPF_MW_SIZE(idx)); + } else { + offset =3D idx =3D=3D 0 ? readl(ndev->ctrl_reg + NTB_EPF_MW1_OFFSET) : 0; + mw_size =3D bar_sz - offset; + } + + if (!mw_size || offset + mw_size > bar_sz) + return -EINVAL; + if (base) *base =3D pci_resource_start(ndev->ntb.pdev, bar) + offset; =20 if (size) - *size =3D pci_resource_len(ndev->ntb.pdev, bar) - offset; + *size =3D mw_size; =20 return 0; } @@ -610,14 +659,61 @@ static inline void ntb_epf_init_struct(struct ntb_epf= _dev *ndev, ndev->ntb.ops =3D &ntb_epf_ops; } =20 +static int ntb_epf_parse_ctrl_version(struct ntb_epf_dev *ndev) +{ + struct device *dev =3D ndev->dev; + u32 ver; + + ver =3D readl(ndev->ctrl_reg + NTB_EPF_CTRL_VERSION); + switch (ver) { + case NTB_EPF_CTRL_VERSION_LEGACY: + case NTB_EPF_CTRL_VERSION_V1: + ndev->ctrl_version =3D ver; + return 0; + default: + dev_err(dev, "Unsupported NTB EPF control version %u\n", ver); + return -EINVAL; + } +} + +static void ntb_epf_parse_dma_locator(struct ntb_epf_dev *ndev) +{ + if (ndev->ctrl_version < NTB_EPF_CTRL_VERSION_V1) { + ndev->dma_abi =3D 0; + ndev->dma_bar =3D NO_BAR; + ndev->dma_offset =3D 0; + ndev->dma_size =3D 0; + ndev->dma_irq_count =3D 0; + return; + } + + ndev->dma_abi =3D readl(ndev->ctrl_reg + NTB_EPF_DMA_ABI); + ndev->dma_bar =3D readl(ndev->ctrl_reg + NTB_EPF_DMA_BAR); + ndev->dma_offset =3D readl(ndev->ctrl_reg + NTB_EPF_DMA_OFFSET); + ndev->dma_size =3D readl(ndev->ctrl_reg + NTB_EPF_DMA_SIZE); + ndev->dma_num_chans =3D readl(ndev->ctrl_reg + NTB_EPF_DMA_NUM_CHANS); + if (ndev->dma_abi && !ndev->dma_num_chans) + ndev->dma_num_chans =3D 1; + ndev->dma_irq_count =3D ndev->dma_num_chans; +} + static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) { struct device *dev =3D ndev->dev; int ret; =20 - /* One Link interrupt and rest doorbell interrupt */ + ret =3D ntb_epf_parse_ctrl_version(ndev); + if (ret) + return ret; + + ntb_epf_parse_dma_locator(ndev); + + /* + * One Link interrupt and rest doorbell interrupt. + * Remote DMA interrupt is best effort. + */ ret =3D ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + 1, - NTB_EPF_MAX_DB_COUNT + 1); + NTB_EPF_MAX_DB_COUNT + 1 + ndev->dma_irq_count); if (ret) { dev_err(dev, "Failed to init ISR\n"); return ret; --=20 2.51.0 From nobody Tue Apr 7 14:41:20 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11021104.outbound.protection.outlook.com [40.107.74.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A99F63FE351; Thu, 12 Mar 2026 16:50:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" When the peer advertises exported DMA ABI v1, create an auxiliary child device named "ep_dma_v1" and pass the parsed locator and IRQ information via a software node. Register the child only after LINK_UP succeeds so the provider is not probed before the remote BAR layout is live, and tear it down again on link down or device removal. This gives controller-specific frontends a clean attachment point without teaching ntb_hw_epf about any particular DMA engine. Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/Kconfig | 1 + drivers/ntb/hw/epf/ntb_hw_epf.c | 87 +++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/ntb/hw/epf/Kconfig b/drivers/ntb/hw/epf/Kconfig index 314485574bf8..03139d6eddc8 100644 --- a/drivers/ntb/hw/epf/Kconfig +++ b/drivers/ntb/hw/epf/Kconfig @@ -1,5 +1,6 @@ config NTB_EPF tristate "Generic EPF Non-Transparent Bridge support" + select AUXILIARY_BUS help This driver supports EPF NTB on configurable endpoint. If unsure, say N. diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index 6b427577b1bd..31f1d3bdffc9 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -7,9 +7,13 @@ */ =20 #include +#include +#include #include +#include #include #include +#include #include #include =20 @@ -75,6 +79,8 @@ =20 #define NTB_EPF_COMMAND_TIMEOUT 1000 /* 1 Sec */ =20 +static DEFINE_IDA(dma_aux_ids); + enum pci_barno { NO_BAR =3D -1, BAR_0, @@ -124,6 +130,8 @@ struct ntb_epf_dev { u32 dma_irq_count; enum pci_barno dma_bar; bool dma_aux_avail; + bool dma_aux_added; + struct auxiliary_device *dma_auxdev; =20 void __iomem *ctrl_reg; void __iomem *db_reg; @@ -138,6 +146,78 @@ struct ntb_epf_dev { =20 #define ntb_ndev(__ntb) container_of(__ntb, struct ntb_epf_dev, ntb) =20 +static void ntb_epf_dma_aux_release(struct device *dev) +{ + struct auxiliary_device *auxdev =3D to_auxiliary_dev(dev); + + kfree(auxdev); +} + +static int ntb_epf_register_dma_auxdev(struct ntb_epf_dev *ndev) +{ + const struct property_entry props[] =3D { + PROPERTY_ENTRY_U32("dma-abi", ndev->dma_abi), + PROPERTY_ENTRY_U32("dma-bar", ndev->dma_bar), + PROPERTY_ENTRY_U32("dma-offset", ndev->dma_offset), + PROPERTY_ENTRY_U32("dma-size", ndev->dma_size), + PROPERTY_ENTRY_U32("dma-num-chans", ndev->dma_num_chans), + PROPERTY_ENTRY_U32("dma-irq-base", ndev->dma_irq_base), + PROPERTY_ENTRY_U32("dma-irq-count", ndev->dma_irq_count), + { } + }; + int ret; + + if (!ndev->dma_aux_avail || ndev->dma_abi !=3D 1 || ndev->dma_aux_added) + return 0; + + struct auxiliary_device *auxdev __free(kfree) =3D kzalloc_obj(*auxdev); + if (!auxdev) + return -ENOMEM; + + ret =3D ida_alloc(&dma_aux_ids, GFP_KERNEL); + if (ret < 0) + return ret; + + auxdev->name =3D "ep_dma_v1"; + auxdev->id =3D ret; + auxdev->dev.parent =3D ndev->dev; + auxdev->dev.release =3D ntb_epf_dma_aux_release; + + ret =3D auxiliary_device_init(auxdev); + if (ret) + goto err_free_id; + + auxdev->dev.dma_parms =3D ndev->dev->dma_parms; + + ret =3D device_create_managed_software_node(&auxdev->dev, props, NULL); + if (ret) + goto err_uninit; + + ret =3D auxiliary_device_add(auxdev); + if (ret) + goto err_uninit; + + ndev->dma_aux_added =3D true; + ndev->dma_auxdev =3D no_free_ptr(auxdev); + return 0; + +err_uninit: + auxiliary_device_uninit(auxdev); +err_free_id: + ida_free(&dma_aux_ids, auxdev->id); + return ret; +} + +static void ntb_epf_unregister_dma_auxdev(struct ntb_epf_dev *ndev) +{ + if (!ndev->dma_aux_added) + return; + + auxiliary_device_delete(ndev->dma_auxdev); + auxiliary_device_uninit(ndev->dma_auxdev); + ndev->dma_aux_added =3D false; +} + static int ntb_epf_send_command(struct ntb_epf_dev *ndev, u32 command, u32 argument) { @@ -337,6 +417,10 @@ static int ntb_epf_link_enable(struct ntb_dev *ntb, return ret; } =20 + ret =3D ntb_epf_register_dma_auxdev(ndev); + if (ret) + dev_warn(dev, "Failed to register DMA auxiliary device\n"); + return 0; } =20 @@ -346,6 +430,8 @@ static int ntb_epf_link_disable(struct ntb_dev *ntb) struct device *dev =3D ndev->dev; int ret; =20 + ntb_epf_unregister_dma_auxdev(ndev); + ret =3D ntb_epf_send_command(ndev, CMD_LINK_DOWN, 0); if (ret) { dev_err(dev, "Fail to disable link\n"); @@ -891,6 +977,7 @@ static void ntb_epf_pci_remove(struct pci_dev *pdev) { struct ntb_epf_dev *ndev =3D pci_get_drvdata(pdev); =20 + ntb_epf_unregister_dma_auxdev(ndev); ntb_unregister_device(&ndev->ntb); ntb_epf_cleanup_isr(ndev); ntb_epf_deinit_pci(ndev); --=20 2.51.0 From nobody Tue Apr 7 14:41:20 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11021077.outbound.protection.outlook.com [52.101.125.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE533FE34A; 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charset="utf-8" Add a small auxiliary-bus frontend that binds to the DMA child created by ntb_hw_epf when a peer advertises exported DMA ABI v1. The frontend reads the ABI header from the exported BAR slice, wires the controller register window and per-channel descriptor windows into a struct dw_edma_chip, and then calls into the common dw-edma core. Use the parent PCI device as chip->dev so IRQ lookup and MSI message composition continue to use the vectors owned by the NTB PCI function. Default delegated channels to remote interrupt delivery. Signed-off-by: Koichiro Den --- drivers/dma/dw-edma/Kconfig | 11 ++ drivers/dma/dw-edma/Makefile | 1 + drivers/dma/dw-edma/dw-edma-aux.c | 297 ++++++++++++++++++++++++++++++ 3 files changed, 309 insertions(+) create mode 100644 drivers/dma/dw-edma/dw-edma-aux.c diff --git a/drivers/dma/dw-edma/Kconfig b/drivers/dma/dw-edma/Kconfig index 2b6f2679508d..a31f6bd784c2 100644 --- a/drivers/dma/dw-edma/Kconfig +++ b/drivers/dma/dw-edma/Kconfig @@ -19,4 +19,15 @@ config DW_EDMA_PCIE eDMA controller and an endpoint PCIe device. This also serves as a reference design to whom desires to use this IP. =20 +config DW_EDMA_AUX + tristate "Synopsys DesignWare eDMA auxiliary-bus frontend" + depends on AUXILIARY_BUS + help + Build a frontend for an endpoint-integrated Synopsys + DesignWare eDMA controller discovered through an auxiliary + device, such as the child created by ntb_hw_epf for an + endpoint DMA engine exported through vNTB. The driver maps the + exported control and descriptor windows and registers the + remote engine with DMAEngine. + endif # DW_EDMA diff --git a/drivers/dma/dw-edma/Makefile b/drivers/dma/dw-edma/Makefile index 83ab58f87760..2545ce4a1989 100644 --- a/drivers/dma/dw-edma/Makefile +++ b/drivers/dma/dw-edma/Makefile @@ -7,3 +7,4 @@ dw-edma-objs :=3D dw-edma-core.o \ dw-edma-v0-core.o \ dw-hdma-v0-core.o $(dw-edma-y) obj-$(CONFIG_DW_EDMA_PCIE) +=3D dw-edma-pcie.o +obj-$(CONFIG_DW_EDMA_AUX) +=3D dw-edma-aux.o diff --git a/drivers/dma/dw-edma/dw-edma-aux.c b/drivers/dma/dw-edma/dw-edm= a-aux.c new file mode 100644 index 000000000000..a7481fa289d0 --- /dev/null +++ b/drivers/dma/dw-edma/dw-edma-aux.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare eDMA auxiliary-bus frontend + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dw_edma_aux { + struct list_head node; + struct pci_dev *pdev; + struct dw_edma_chip chip; + void __iomem *bar_base; + void __iomem *ctrl_base; + u32 irq_base; +}; + +static DEFINE_MUTEX(dw_edma_aux_lock); +static LIST_HEAD(dw_edma_aux_list); + +static struct dw_edma_aux *dw_edma_aux_find_by_pdev(struct pci_dev *pdev) +{ + struct dw_edma_aux *aux; + + list_for_each_entry(aux, &dw_edma_aux_list, node) + if (aux->pdev =3D=3D pdev) + return aux; + + return NULL; +} + +static int dw_edma_aux_register(struct dw_edma_aux *aux) +{ + int ret =3D 0; + + mutex_lock(&dw_edma_aux_lock); + if (dw_edma_aux_find_by_pdev(aux->pdev)) + ret =3D -EEXIST; + else + list_add_tail(&aux->node, &dw_edma_aux_list); + mutex_unlock(&dw_edma_aux_lock); + + return ret; +} + +static void dw_edma_aux_unregister(struct dw_edma_aux *aux) +{ + mutex_lock(&dw_edma_aux_lock); + if (!list_empty(&aux->node)) + list_del_init(&aux->node); + mutex_unlock(&dw_edma_aux_lock); +} + +static bool dw_edma_aux_region_valid(u32 dma_off, u32 dma_sz, u32 off, u32= sz) +{ + u32 rel; + + if (off < dma_off || !sz) + return false; + + rel =3D off - dma_off; + if (rel > dma_sz) + return false; + + return sz <=3D dma_sz - rel; +} + +static int dw_edma_aux_irq_vector(struct device *dev, unsigned int nr) +{ + struct dw_edma_aux *aux; + int irq =3D -ENODEV; + + mutex_lock(&dw_edma_aux_lock); + aux =3D dw_edma_aux_find_by_pdev(to_pci_dev(dev)); + if (aux) + irq =3D pci_irq_vector(aux->pdev, aux->irq_base + nr); + mutex_unlock(&dw_edma_aux_lock); + + return irq; +} + +static const struct dw_edma_plat_ops dw_edma_aux_plat_ops =3D { + .irq_vector =3D dw_edma_aux_irq_vector, +}; + +static int dw_edma_aux_probe(struct auxiliary_device *auxdev, + const struct auxiliary_device_id *id) +{ + void __iomem *base, *ctrl_base =3D NULL, *reg_base =3D NULL; + struct device *dev =3D &auxdev->dev; + struct pci_dev *pdev =3D to_pci_dev(dev->parent); + struct pci_ep_dma_hdr_v1 hdr; + struct dw_edma_chip *chip; + struct dw_edma_aux *aux; + u32 dma_abi, dma_bar, dma_offset, dma_size; + u32 desc_bar, desc_offset, desc_size; + u32 ctrl_bar, ctrl_offset, ctrl_size; + u32 irq_base, irq_count, num_chans; + u16 hdr_size, total_size; + u32 hdr_irq_count; + unsigned int i; + int ret; + + ret =3D device_property_read_u32(dev, "dma-abi", &dma_abi); + if (ret) + return ret; + if (dma_abi !=3D PCI_EP_DMA_ABI_V1) + return -EINVAL; + + ret =3D device_property_read_u32(dev, "dma-bar", &dma_bar); + if (ret) + return ret; + ret =3D device_property_read_u32(dev, "dma-offset", &dma_offset); + if (ret) + return ret; + ret =3D device_property_read_u32(dev, "dma-size", &dma_size); + if (ret) + return ret; + if (dma_bar > BAR_5 || !dma_size) + return -EINVAL; + if (dma_size < sizeof(hdr)) + return -EINVAL; + ret =3D device_property_read_u32(dev, "dma-irq-base", &irq_base); + if (ret) + return ret; + ret =3D device_property_read_u32(dev, "dma-irq-count", &irq_count); + if (ret) + return ret; + if (!irq_count) + return -EINVAL; + + base =3D pci_iomap_range(pdev, dma_bar, dma_offset, dma_size); + if (!base) + return -ENOMEM; + + memcpy_fromio(&hdr, base, sizeof(hdr)); + if (le32_to_cpu(hdr.magic) !=3D PCI_EP_DMA_MAGIC) { + ret =3D -EINVAL; + goto err_iounmap; + } + if (le16_to_cpu(hdr.version) !=3D 1) { + ret =3D -EINVAL; + goto err_iounmap; + } + + hdr_size =3D le16_to_cpu(hdr.hdr_size); + total_size =3D le32_to_cpu(hdr.total_size); + hdr_irq_count =3D le32_to_cpu(hdr.irq_count); + if (hdr_size !=3D sizeof(hdr) || total_size !=3D dma_size || + hdr_irq_count !=3D irq_count) { + ret =3D -EINVAL; + goto err_iounmap; + } + + ctrl_bar =3D le32_to_cpu(hdr.ctrl_bar); + ctrl_offset =3D le32_to_cpu(hdr.ctrl_offset); + ctrl_size =3D le32_to_cpu(hdr.ctrl_size); + num_chans =3D le32_to_cpu(hdr.num_chans); + if (!num_chans || num_chans > PCI_EP_DMA_MAX_CHANS || + num_chans > irq_count) { + ret =3D -EINVAL; + goto err_iounmap; + } + + if (!ctrl_size || ctrl_bar > BAR_5) { + ret =3D -EINVAL; + goto err_iounmap; + } + + /* + * The exported DMA window is only guaranteed to cover the locator and + * descriptor subranges. The live eDMA register block may be advertised + * through another BAR, or elsewhere in the same BAR, and must then be + * mapped directly. + */ + if (ctrl_bar =3D=3D dma_bar && + dw_edma_aux_region_valid(dma_offset, dma_size, ctrl_offset, + ctrl_size)) { + ctrl_base =3D NULL; + reg_base =3D base + (ctrl_offset - dma_offset); + } else { + ctrl_base =3D pci_iomap_range(pdev, ctrl_bar, ctrl_offset, + ctrl_size); + if (!ctrl_base) { + ret =3D -ENOMEM; + goto err_iounmap; + } + reg_base =3D ctrl_base; + } + + for (i =3D 0; i < num_chans; i++) { + desc_bar =3D le32_to_cpu(hdr.chans[i].desc_bar); + desc_offset =3D le32_to_cpu(hdr.chans[i].desc_offset); + desc_size =3D le32_to_cpu(hdr.chans[i].desc_size); + if (desc_bar !=3D dma_bar || + !dw_edma_aux_region_valid(dma_offset, dma_size, desc_offset, + desc_size)) { + ret =3D -EINVAL; + goto err_ctrl_iounmap; + } + } + + aux =3D devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL); + if (!aux) { + ret =3D -ENOMEM; + goto err_ctrl_iounmap; + } + + INIT_LIST_HEAD(&aux->node); + aux->pdev =3D pdev; + aux->bar_base =3D base; + aux->ctrl_base =3D ctrl_base; + aux->irq_base =3D irq_base; + + ret =3D dw_edma_aux_register(aux); + if (ret) + goto err_ctrl_iounmap; + + chip =3D &aux->chip; + chip->dev =3D dev->parent; + chip->nr_irqs =3D irq_count; + chip->ops =3D &dw_edma_aux_plat_ops; + chip->flags =3D 0; + chip->mf =3D EDMA_MF_EDMA_UNROLL; + chip->default_irq_mode =3D DW_EDMA_CH_IRQ_REMOTE; + chip->reg_base =3D reg_base; + chip->ll_wr_cnt =3D 0; + /* + * ABI v1 exports READ channels only. @hdr->chans[] is defined as a dense + * prefix of the remote hardware READ-channel space, ordered by remote + * hardware READ-channel index starting at 0, so ll_region_rd[i] can be + * consumed as local READ channel i. + */ + chip->ll_rd_cnt =3D num_chans; + for (i =3D 0; i < num_chans; i++) { + desc_offset =3D le32_to_cpu(hdr.chans[i].desc_offset); + desc_size =3D le32_to_cpu(hdr.chans[i].desc_size); + chip->ll_region_rd[i].vaddr.io =3D base + (desc_offset - dma_offset); + chip->ll_region_rd[i].paddr =3D le64_to_cpu(hdr.chans[i].desc_phys_addr); + chip->ll_region_rd[i].sz =3D desc_size; + } + + dev_set_drvdata(dev, aux); + ret =3D dw_edma_probe(chip); + if (ret) { + dw_edma_aux_unregister(aux); + goto err_ctrl_iounmap; + } + + return 0; + +err_ctrl_iounmap: + if (ctrl_base) + pci_iounmap(pdev, ctrl_base); +err_iounmap: + pci_iounmap(pdev, base); + return ret; +} + +static void dw_edma_aux_remove(struct auxiliary_device *auxdev) +{ + struct dw_edma_aux *aux =3D dev_get_drvdata(&auxdev->dev); + + if (!aux) + return; + + dw_edma_remove(&aux->chip); + dw_edma_aux_unregister(aux); + if (aux->ctrl_base) + pci_iounmap(aux->pdev, aux->ctrl_base); + pci_iounmap(aux->pdev, aux->bar_base); +} + +static const struct auxiliary_device_id dw_edma_aux_ids[] =3D { + { .name =3D "ntb_hw_epf.ep_dma_v1" }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, dw_edma_aux_ids); + +static struct auxiliary_driver dw_edma_aux_driver =3D { + .name =3D "dw_edma_aux", + .probe =3D dw_edma_aux_probe, + .remove =3D dw_edma_aux_remove, + .id_table =3D dw_edma_aux_ids, +}; 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Thu, 12 Mar 2026 16:50:22 +0000 From: Koichiro Den To: Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Shuah Khan , Vinod Koul , Frank Li , Jon Mason , Dave Jiang , Allen Hubbe , Jingoo Han , Lorenzo Pieralisi , Rob Herring , Baruch Siach , Jerome Brunet , Niklas Cassel Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, ntb@lists.linux.dev Subject: [PATCH 14/15] NTB: Add ntb_ep_dma test client Date: Fri, 13 Mar 2026 01:50:04 +0900 Message-ID: <20260312165005.1148676-15-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260312165005.1148676-1-den@valinux.co.jp> References: <20260312165005.1148676-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP301CA0067.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:7d::20) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB7722:EE_|TYCP286MB2018:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d45b3fe-eb2c-47d5-dcac-08de80577393 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|10070799003|366016|7416014|921020|56012099003|22082099003|18002099003; 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charset="utf-8" Add a small NTB client that exercises an endpoint-integrated DMA engine exported through vNTB. Both peers allocate a coherent test buffer and publish its DMA address and size through scratchpads. The initiator requests the remote DMA engine provider and uses it to transfer a known pattern into the peer-published buffer. The responder verifies the contents locally and reports PASS or FAIL back through scratchpads and a doorbell. Expose ready, run, and result files in debugfs to make the flow easy to trigger during bring-up. Signed-off-by: Koichiro Den --- drivers/ntb/test/Kconfig | 10 + drivers/ntb/test/Makefile | 1 + drivers/ntb/test/ntb_ep_dma.c | 695 ++++++++++++++++++++++++++++++++++ 3 files changed, 706 insertions(+) create mode 100644 drivers/ntb/test/ntb_ep_dma.c diff --git a/drivers/ntb/test/Kconfig b/drivers/ntb/test/Kconfig index 516b991f33b9..30d0fede968c 100644 --- a/drivers/ntb/test/Kconfig +++ b/drivers/ntb/test/Kconfig @@ -35,3 +35,13 @@ config NTB_MSI_TEST send MSI interrupts between peers. =20 If unsure, say N. + +config NTB_EP_DMA + tristate "NTB EP DMA Test Client" + help + This test client demonstrates the use of an endpoint-integrated DMA + engine exported through vNTB. It is intended as a simple bring-up and + end-to-end validation tool for the remote-DMA discovery and transfer + path. + + If unsure, say N. diff --git a/drivers/ntb/test/Makefile b/drivers/ntb/test/Makefile index 19ed91d8a3b1..f5bd0a85d4c8 100644 --- a/drivers/ntb/test/Makefile +++ b/drivers/ntb/test/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_NTB_PINGPONG) +=3D ntb_pingpong.o obj-$(CONFIG_NTB_TOOL) +=3D ntb_tool.o obj-$(CONFIG_NTB_PERF) +=3D ntb_perf.o obj-$(CONFIG_NTB_MSI_TEST) +=3D ntb_msi_test.o +obj-$(CONFIG_NTB_EP_DMA) +=3D ntb_ep_dma.o diff --git a/drivers/ntb/test/ntb_ep_dma.c b/drivers/ntb/test/ntb_ep_dma.c new file mode 100644 index 000000000000..7cee158369a1 --- /dev/null +++ b/drivers/ntb/test/ntb_ep_dma.c @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Koichiro Den "); +MODULE_DESCRIPTION("Test for using EPC-integrated DMA engine remotely"); + +#define NTB_EP_DMA_BUF_LEN SZ_4K +#define NTB_EP_DMA_TIMEOUT_MS 5000 +#define NTB_EP_DMA_TIMEOUT msecs_to_jiffies(NTB_EP_DMA_TIMEOUT_MS) + +#define NTB_EP_DMA_SPAD_STATE 0 +#define NTB_EP_DMA_SPAD_ADDR_LO 1 +#define NTB_EP_DMA_SPAD_ADDR_HI 2 +#define NTB_EP_DMA_SPAD_SIZE 3 +#define NTB_EP_DMA_SPAD_SEQ 4 +#define NTB_EP_DMA_SPAD_XFER_LEN 5 +#define NTB_EP_DMA_SPAD_CNT 6 + +/* + * Test protocol: + * - both peers publish a local coherent buffer through scratchpads and + * ring a doorbell when READY + * - the initiator submits one transfer through the remote DMA provider + * - the responder verifies the pattern locally and reports PASS/FAIL + * back through scratchpads and a doorbell + */ +enum ntb_ep_dma_state { + NTB_EP_DMA_ST_INIT =3D 0, + NTB_EP_DMA_ST_READY, + NTB_EP_DMA_ST_XFER_DONE, + NTB_EP_DMA_ST_PASS, + NTB_EP_DMA_ST_FAIL, +}; + +struct ntb_ep_dma_peer { + dma_addr_t dma_addr; + u32 size; + u32 state; + u32 seq; + u32 xfer_len; +}; + +struct ntb_ep_dma_ctx { + struct ntb_dev *ntb; + struct dentry *dbgfs_dir; + /* Serialize userspace-triggered runs through debugfs. */ + struct mutex run_lock; + /* Protect peer state and completion sequencing shared with db_event. */ + spinlock_t lock; + struct work_struct setup_work; + struct work_struct verify_work; + struct completion peer_ready; + struct completion xfer_done; + + struct device *buf_dev; + void *buf; + dma_addr_t buf_dma; + size_t buf_size; + + struct ntb_ep_dma_peer peer; + u32 local_seq; + u32 done_seq; + u32 verify_seq; + u32 verify_len; + u32 verified_seq; + + size_t last_len; + int last_status; +}; + +static struct dentry *ntb_ep_dma_dbgfs_topdir; + +static const char *ntb_ep_dma_state_name(u32 state) +{ + switch (state) { + case NTB_EP_DMA_ST_INIT: + return "init"; + case NTB_EP_DMA_ST_READY: + return "ready"; + case NTB_EP_DMA_ST_XFER_DONE: + return "xfer-done"; + case NTB_EP_DMA_ST_PASS: + return "pass"; + case NTB_EP_DMA_ST_FAIL: + return "fail"; + default: + return "unknown"; + } +} + +static void ntb_ep_dma_fill_pattern(void *buf, size_t len) +{ + u8 *ptr =3D buf; + size_t i; + + for (i =3D 0; i < len; i++) + ptr[i] =3D (u8)i; +} + +static int ntb_ep_dma_verify_pattern(const void *buf, size_t len) +{ + const u8 *ptr =3D buf; + size_t i; + + for (i =3D 0; i < len; i++) { + if (ptr[i] !=3D (u8)i) + return -EIO; + } + + return 0; +} + +static int ntb_ep_dma_signal_peer(struct ntb_ep_dma_ctx *ctx) +{ + return ntb_peer_db_set(ctx->ntb, BIT_ULL(ntb_port_number(ctx->ntb))); +} + +static int ntb_ep_dma_publish(struct ntb_ep_dma_ctx *ctx, u32 state, u32 s= eq, + u32 xfer_len) +{ + int ret; + + ret =3D ntb_spad_write(ctx->ntb, NTB_EP_DMA_SPAD_STATE, state); + if (ret) + return ret; + + ret =3D ntb_spad_write(ctx->ntb, NTB_EP_DMA_SPAD_ADDR_LO, + lower_32_bits(ctx->buf_dma)); + if (ret) + return ret; + + ret =3D ntb_spad_write(ctx->ntb, NTB_EP_DMA_SPAD_ADDR_HI, + upper_32_bits(ctx->buf_dma)); + if (ret) + return ret; + + ret =3D ntb_spad_write(ctx->ntb, NTB_EP_DMA_SPAD_SIZE, ctx->buf_size); + if (ret) + return ret; + + ret =3D ntb_spad_write(ctx->ntb, NTB_EP_DMA_SPAD_SEQ, seq); + if (ret) + return ret; + + return ntb_spad_write(ctx->ntb, NTB_EP_DMA_SPAD_XFER_LEN, xfer_len); +} + +static struct ntb_ep_dma_peer +ntb_ep_dma_read_peer(struct ntb_ep_dma_ctx *ctx) +{ + struct ntb_ep_dma_peer peer; + u32 hi, lo; + + peer.state =3D ntb_peer_spad_read(ctx->ntb, 0, NTB_EP_DMA_SPAD_STATE); + lo =3D ntb_peer_spad_read(ctx->ntb, 0, NTB_EP_DMA_SPAD_ADDR_LO); + hi =3D ntb_peer_spad_read(ctx->ntb, 0, NTB_EP_DMA_SPAD_ADDR_HI); + peer.dma_addr =3D ((u64)hi << 32) | lo; + peer.size =3D ntb_peer_spad_read(ctx->ntb, 0, NTB_EP_DMA_SPAD_SIZE); + peer.seq =3D ntb_peer_spad_read(ctx->ntb, 0, NTB_EP_DMA_SPAD_SEQ); + peer.xfer_len =3D ntb_peer_spad_read(ctx->ntb, 0, + NTB_EP_DMA_SPAD_XFER_LEN); + + return peer; +} + +static bool ntb_ep_dma_filter(struct dma_chan *chan, void *data) +{ + struct ntb_ep_dma_ctx *ctx =3D data; + struct device *dev; + + dev =3D dmaengine_get_dma_device(chan); + if (!dev || !dev->parent) + return false; + + return dev =3D=3D ntb_get_dma_dev(ctx->ntb); +} + +static void ntb_ep_dma_done(void *arg) +{ + complete(arg); +} + +static int ntb_ep_dma_submit_xfer(struct ntb_ep_dma_ctx *ctx, + dma_addr_t peer_dma, size_t len) +{ + struct dma_async_tx_descriptor *tx; + struct dma_slave_config cfg =3D {}; + struct completion done; + struct device *dma_dev; + struct dma_chan *chan; + dma_cap_mask_t mask; + dma_cookie_t cookie; + dma_addr_t src_dma; + void *src_buf; + int ret =3D 0; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + + chan =3D dma_request_channel(mask, ntb_ep_dma_filter, ctx); + if (!chan) + return -ENODEV; + + dma_dev =3D ntb_get_dma_dev(ctx->ntb); + if (!dma_dev) { + ret =3D -ENODEV; + goto err_release_chan; + } + + src_buf =3D dma_alloc_coherent(dma_dev, len, &src_dma, GFP_KERNEL); + if (!src_buf) { + ret =3D -ENOMEM; + goto err_release_chan; + } + + ntb_ep_dma_fill_pattern(src_buf, len); + dma_wmb(); + + cfg.dst_addr =3D peer_dma; + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.direction =3D DMA_MEM_TO_DEV; + + ret =3D dmaengine_slave_config(chan, &cfg); + if (ret) + goto err_free_src; + + tx =3D dmaengine_prep_slave_single(chan, src_dma, len, + DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!tx) { + ret =3D -EIO; + goto err_free_src; + } + + init_completion(&done); + tx->callback =3D ntb_ep_dma_done; + tx->callback_param =3D &done; + + cookie =3D dmaengine_submit(tx); + ret =3D dma_submit_error(cookie); + if (ret) + goto err_free_src; + + dma_async_issue_pending(chan); + + if (!wait_for_completion_timeout(&done, NTB_EP_DMA_TIMEOUT)) { + ret =3D -ETIMEDOUT; + dmaengine_terminate_sync(chan); + } + +err_free_src: + dma_free_coherent(dma_dev, len, src_buf, src_dma); +err_release_chan: + dma_release_channel(chan); + + return ret; +} + +static void ntb_ep_dma_verify_work(struct work_struct *work) +{ + struct ntb_ep_dma_ctx *ctx =3D + container_of(work, struct ntb_ep_dma_ctx, verify_work); + u32 seq, len, state; + int ret; + + scoped_guard(spinlock_irqsave, &ctx->lock) { + seq =3D ctx->verify_seq; + len =3D ctx->verify_len; + } + + if (!ctx->buf || len > ctx->buf_size) + ret =3D -EMSGSIZE; + else + ret =3D ntb_ep_dma_verify_pattern(ctx->buf, len); + + state =3D ret ? NTB_EP_DMA_ST_FAIL : NTB_EP_DMA_ST_PASS; + + scoped_guard(spinlock_irqsave, &ctx->lock) { + ctx->verified_seq =3D seq; + ctx->last_status =3D ret; + ctx->last_len =3D len; + } + + ret =3D ntb_ep_dma_publish(ctx, state, seq, len); + if (!ret) + ret =3D ntb_ep_dma_signal_peer(ctx); + if (ret) + dev_err(&ctx->ntb->dev, "failed to publish verify result: %d\n", + ret); +} + +static void ntb_ep_dma_try_capture_peer_ready(struct ntb_ep_dma_ctx *ctx) +{ + struct ntb_ep_dma_peer peer =3D ntb_ep_dma_read_peer(ctx); + + guard(spinlock_irqsave)(&ctx->lock); + + ctx->peer =3D peer; + if (peer.state >=3D NTB_EP_DMA_ST_READY && + peer.dma_addr && peer.size) + complete_all(&ctx->peer_ready); +} + +static void ntb_ep_dma_setup_work(struct work_struct *work) +{ + struct ntb_ep_dma_ctx *ctx =3D + container_of(work, struct ntb_ep_dma_ctx, setup_work); + struct device *dma_dev; + int ret; + + if (!ntb_link_is_up(ctx->ntb, NULL, NULL)) + return; + + if (!ctx->buf) { + dma_dev =3D ntb_get_dma_dev(ctx->ntb); + if (!dma_dev) { + dev_err(&ctx->ntb->dev, + "no DMA mapping device available\n"); + return; + } + + ctx->buf =3D dma_alloc_coherent(dma_dev, ctx->buf_size, + &ctx->buf_dma, GFP_KERNEL); + if (!ctx->buf) + return; + + ctx->buf_dev =3D dma_dev; + } + + memset(ctx->buf, 0, ctx->buf_size); + reinit_completion(&ctx->peer_ready); + + ret =3D ntb_ep_dma_publish(ctx, NTB_EP_DMA_ST_READY, 0, 0); + if (ret) + goto err_free_buf; + + ntb_ep_dma_try_capture_peer_ready(ctx); + + ret =3D ntb_ep_dma_signal_peer(ctx); + if (ret) + goto err_free_buf; + + return; + +err_free_buf: + dev_err(&ctx->ntb->dev, "failed to publish READY state: %d\n", ret); + dma_free_coherent(ctx->buf_dev, ctx->buf_size, ctx->buf, ctx->buf_dma); + ctx->buf =3D NULL; + ctx->buf_dev =3D NULL; + ctx->buf_dma =3D 0; +} + +static void ntb_ep_dma_link_event(void *data) +{ + struct ntb_ep_dma_ctx *ctx =3D data; + + if (!ntb_link_is_up(ctx->ntb, NULL, NULL)) + return; + + schedule_work(&ctx->setup_work); +} + +static void ntb_ep_dma_db_event(void *data, int vec) +{ + struct ntb_ep_dma_ctx *ctx =3D data; + struct ntb_ep_dma_peer peer; + bool do_complete =3D false; + bool do_verify =3D false; + u64 db_bits; + + db_bits =3D ntb_db_read(ctx->ntb); + if (!db_bits) + return; + + ntb_db_clear(ctx->ntb, db_bits); + + peer =3D ntb_ep_dma_read_peer(ctx); + + scoped_guard(spinlock_irqsave, &ctx->lock) { + ctx->peer =3D peer; + if (peer.state >=3D NTB_EP_DMA_ST_READY && peer.dma_addr && + peer.size) + complete_all(&ctx->peer_ready); + + if (peer.state =3D=3D NTB_EP_DMA_ST_XFER_DONE && + peer.seq !=3D ctx->verified_seq) { + ctx->verify_seq =3D peer.seq; + ctx->verify_len =3D peer.xfer_len; + do_verify =3D true; + } else if ((peer.state =3D=3D NTB_EP_DMA_ST_PASS || + peer.state =3D=3D NTB_EP_DMA_ST_FAIL) && + peer.seq =3D=3D ctx->local_seq && + peer.seq !=3D ctx->done_seq) { + ctx->done_seq =3D peer.seq; + do_complete =3D true; + } + } + + if (do_verify) + schedule_work(&ctx->verify_work); + if (do_complete) + complete_all(&ctx->xfer_done); +} + +static const struct ntb_ctx_ops ntb_ep_dma_ops =3D { + .link_event =3D ntb_ep_dma_link_event, + .db_event =3D ntb_ep_dma_db_event, +}; + +static int ntb_ep_dma_ready_get(void *data, u64 *ready) +{ + struct ntb_ep_dma_ctx *ctx =3D data; + + *ready =3D completion_done(&ctx->peer_ready); + return 0; +} + +static int ntb_ep_dma_ready_set(void *data, u64 ready) +{ + struct ntb_ep_dma_ctx *ctx =3D data; + + return wait_for_completion_interruptible(&ctx->peer_ready); +} + +DEFINE_DEBUGFS_ATTRIBUTE(ntb_ep_dma_ready_fops, ntb_ep_dma_ready_get, + ntb_ep_dma_ready_set, "%llu\n"); + +static int ntb_ep_dma_result_show(struct seq_file *s, void *unused) +{ + struct ntb_ep_dma_ctx *ctx =3D s->private; + struct ntb_ep_dma_peer peer; + + guard(spinlock_irqsave)(&ctx->lock); + + peer =3D ctx->peer; + + seq_printf(s, "last_status: %d\n", ctx->last_status); + seq_printf(s, "last_len: %zu\n", ctx->last_len); + seq_printf(s, "local_buf_dma: %#llx\n", ctx->buf_dma); + seq_printf(s, "local_buf_size: %zu\n", ctx->buf_size); + seq_printf(s, "peer_ready: %u\n", completion_done(&ctx->peer_ready)); + seq_printf(s, "peer_state: %s\n", ntb_ep_dma_state_name(peer.state)); + seq_printf(s, "peer_dma: 0x%llx\n", peer.dma_addr); + seq_printf(s, "peer_size: %u\n", peer.size); + seq_printf(s, "peer_seq: %u\n", peer.seq); + seq_printf(s, "peer_xfer_len: %u\n", peer.xfer_len); + seq_printf(s, "link_up: %u\n", !!ntb_link_is_up(ctx->ntb, NULL, NULL)); + + return 0; +} + +static int ntb_ep_dma_result_open(struct inode *inode, struct file *file) +{ + return single_open(file, ntb_ep_dma_result_show, inode->i_private); +} + +static int ntb_ep_dma_run_once(struct ntb_ep_dma_ctx *ctx) +{ + struct ntb_ep_dma_peer peer; + size_t len; + int status; + long ret; + u32 seq; + + ret =3D wait_for_completion_interruptible_timeout(&ctx->peer_ready, + NTB_EP_DMA_TIMEOUT); + if (ret < 0) + return ret; + if (!ret) + return -ETIMEDOUT; + + peer =3D ctx->peer; + scoped_guard(spinlock_irqsave, &ctx->lock) { + seq =3D ++ctx->local_seq; + ctx->done_seq =3D 0; + } + + if (!peer.dma_addr || !peer.size) + return -ENXIO; + + len =3D min_t(size_t, ctx->buf_size, peer.size); + if (!len) + return -EMSGSIZE; + + reinit_completion(&ctx->xfer_done); + + status =3D ntb_ep_dma_submit_xfer(ctx, peer.dma_addr, len); + if (status) + return status; + + status =3D ntb_ep_dma_publish(ctx, NTB_EP_DMA_ST_XFER_DONE, seq, len); + if (status) + return status; + + status =3D ntb_ep_dma_signal_peer(ctx); + if (status) + return status; + + ret =3D wait_for_completion_interruptible_timeout(&ctx->xfer_done, + NTB_EP_DMA_TIMEOUT); + if (ret < 0) + return ret; + if (!ret) + return -ETIMEDOUT; + + guard(spinlock_irqsave)(&ctx->lock); + + peer =3D ctx->peer; + + if (peer.seq !=3D seq) + return -EPROTO; + if (peer.state !=3D NTB_EP_DMA_ST_PASS) + return -EIO; + + ctx->last_len =3D len; + return 0; +} + +static ssize_t ntb_ep_dma_run_write(struct file *file, const char __user *= ubuf, + size_t len, loff_t *ppos) +{ + struct ntb_ep_dma_ctx *ctx =3D file->private_data; + unsigned long start; + char buf[32]; + size_t cplen; + int ret; + + if (*ppos) + return -EINVAL; + + cplen =3D min(len, sizeof(buf) - 1); + if (copy_from_user(buf, ubuf, cplen)) + return -EFAULT; + + buf[cplen] =3D '\0'; + strim(buf); + + ret =3D kstrtoul(buf, 0, &start); + if (ret) + return ret; + if (!start) + return -EINVAL; + + guard(mutex)(&ctx->run_lock); + + ret =3D ntb_ep_dma_run_once(ctx); + ctx->last_status =3D ret; + if (ret) + return ret; + + return len; +} + +static const struct file_operations ntb_ep_dma_result_fops =3D { + .owner =3D THIS_MODULE, + .open =3D ntb_ep_dma_result_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static const struct file_operations ntb_ep_dma_run_fops =3D { + .owner =3D THIS_MODULE, + .open =3D simple_open, + .write =3D ntb_ep_dma_run_write, + .llseek =3D noop_llseek, +}; + +static int ntb_ep_dma_check_ntb(struct ntb_dev *ntb) +{ + if (ntb_peer_port_count(ntb) !=3D 1) + return -EINVAL; + + if (ntb_spad_count(ntb) < NTB_EP_DMA_SPAD_CNT) + return -EINVAL; + + return 0; +} + +static int ntb_ep_dma_probe(struct ntb_client *client, struct ntb_dev *ntb) +{ + struct ntb_ep_dma_ctx *ctx; + int ret; + + ret =3D ntb_ep_dma_check_ntb(ntb); + if (ret) + return ret; + + ctx =3D devm_kzalloc(&ntb->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->ntb =3D ntb; + ctx->buf_size =3D NTB_EP_DMA_BUF_LEN; + ctx->last_len =3D 0; + ctx->last_status =3D 0; + ctx->verified_seq =3D U32_MAX; + mutex_init(&ctx->run_lock); + spin_lock_init(&ctx->lock); + init_completion(&ctx->peer_ready); + init_completion(&ctx->xfer_done); + INIT_WORK(&ctx->setup_work, ntb_ep_dma_setup_work); + INIT_WORK(&ctx->verify_work, ntb_ep_dma_verify_work); + + ret =3D ntb_set_ctx(ntb, ctx, &ntb_ep_dma_ops); + if (ret) + return ret; + + ret =3D ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + if (ret) + goto err_clear_ctx; + + if (ntb_link_is_up(ntb, NULL, NULL)) + schedule_work(&ctx->setup_work); + + if (debugfs_initialized()) { + ctx->dbgfs_dir =3D debugfs_create_dir(pci_name(ntb->pdev), + ntb_ep_dma_dbgfs_topdir); + debugfs_create_file("run", 0200, ctx->dbgfs_dir, ctx, + &ntb_ep_dma_run_fops); + debugfs_create_file("result", 0400, ctx->dbgfs_dir, ctx, + &ntb_ep_dma_result_fops); + debugfs_create_file_unsafe("ready", 0600, ctx->dbgfs_dir, ctx, + &ntb_ep_dma_ready_fops); + } + + return 0; + +err_clear_ctx: + ntb_clear_ctx(ntb); + return ret; +} + +static void ntb_ep_dma_remove(struct ntb_client *client, struct ntb_dev *n= tb) +{ + struct ntb_ep_dma_ctx *ctx =3D ntb->ctx; + + debugfs_remove_recursive(ctx->dbgfs_dir); + cancel_work_sync(&ctx->verify_work); + cancel_work_sync(&ctx->setup_work); + if (ctx->buf) + dma_free_coherent(ctx->buf_dev, ctx->buf_size, + ctx->buf, ctx->buf_dma); + ntb_link_disable(ntb); + ntb_clear_ctx(ntb); +} + +static struct ntb_client ntb_ep_dma_client =3D { + .ops =3D { + .probe =3D ntb_ep_dma_probe, + .remove =3D ntb_ep_dma_remove, + }, +}; + +static int __init ntb_ep_dma_init(void) +{ + int ret; + + if (debugfs_initialized()) + ntb_ep_dma_dbgfs_topdir =3D debugfs_create_dir(KBUILD_MODNAME, NULL); + + ret =3D ntb_register_client(&ntb_ep_dma_client); + if (ret) + debugfs_remove_recursive(ntb_ep_dma_dbgfs_topdir); + + return ret; +} +module_init(ntb_ep_dma_init); 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Thu, 12 Mar 2026 16:50:23 +0000 From: Koichiro Den To: Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Shuah Khan , Vinod Koul , Frank Li , Jon Mason , Dave Jiang , Allen Hubbe , Jingoo Han , Lorenzo Pieralisi , Rob Herring , Baruch Siach , Jerome Brunet , Niklas Cassel Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, ntb@lists.linux.dev Subject: [PATCH 15/15] Documentation: PCI: endpoint: Add vNTB DMA export HOWTO Date: Fri, 13 Mar 2026 01:50:05 +0900 Message-ID: <20260312165005.1148676-16-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260312165005.1148676-1-den@valinux.co.jp> References: <20260312165005.1148676-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP301CA0065.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:7d::10) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB7722:EE_|TYCP286MB2018:EE_ X-MS-Office365-Filtering-Correlation-Id: 70c09369-2c57-41b7-93f1-08de80577411 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|10070799003|366016|7416014|921020|56012099003|22082099003|18002099003; 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charset="utf-8" Document the new pci-epf-vntb DMA export model. Describe the configfs placement knobs for the DMA slice, the versioned control layout, the two-stage BAR programming model used for shared BARs, and the host-side discovery path through ntb_hw_epf and dw-edma-aux. Also show how to exercise the feature with the ntb_ep_dma test client. Signed-off-by: Koichiro Den --- Documentation/PCI/endpoint/index.rst | 1 + .../PCI/endpoint/pci-vntb-dma-howto.rst | 83 +++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 Documentation/PCI/endpoint/pci-vntb-dma-howto.rst diff --git a/Documentation/PCI/endpoint/index.rst b/Documentation/PCI/endpo= int/index.rst index dd1f62e731c9..c3f93f1da34b 100644 --- a/Documentation/PCI/endpoint/index.rst +++ b/Documentation/PCI/endpoint/index.rst @@ -15,6 +15,7 @@ PCI Endpoint Framework pci-ntb-howto pci-vntb-function pci-vntb-howto + pci-vntb-dma-howto pci-nvme-function =20 function/binding/pci-test diff --git a/Documentation/PCI/endpoint/pci-vntb-dma-howto.rst b/Documentat= ion/PCI/endpoint/pci-vntb-dma-howto.rst new file mode 100644 index 000000000000..c3acc4e6ab37 --- /dev/null +++ b/Documentation/PCI/endpoint/pci-vntb-dma-howto.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +pci-epf-vntb DMA export HOWTO +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +``pci-epf-vntb`` can expose a virtual NTB device to the host while also +exporting an endpoint-integrated DMA instance. The logical DMA export slic= e may +occupy its own BAR or share a physical BAR with one or more memory windows. + +Configuration knobs +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The endpoint function instance exposes the following placement controls via +configfs: + +- ``mwN_bar`` +- ``mwN_offset`` +- ``dma_bar`` +- ``dma_offset`` +- ``dma_num_chans`` + +The offsets are BAR-relative. Regions packed into the same physical BAR mu= st be +non-overlapping and must cover the complete programmed BAR aperture. + +``dma_num_chans`` controls how many DMA read channels are delegated to the +peer. If fewer channels are available at runtime, the endpoint falls back = to +the maximum available number and reports the effective delegation count in= the +kernel log. + +DMA ABI v1 is currently defined for READ channels only. The exported chann= els +must form a dense prefix of the endpoint READ-channel space, and the +``chans[]`` entries in the ABI header are ordered by remote hardware READ +channel index starting at 0. ``dw-edma-aux`` relies on that ordering when = it +reconstructs the remote engine on the host side. + +Control-layout compatibility +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Offset ``0x0c`` in the control block is used as a control-layout version. = The +legacy layout is version 0. Version 1 extends the block with per-MW +``offset/size`` tuples and the DMA locator. + +``pci-epf-vntb`` emits the legacy layout whenever the current configuratio= n can +still be represented by it. This allows a new endpoint kernel to interoper= ate +with an older ``ntb_hw_epf`` host as long as the deployment uses the histo= rical +one-MW-per-BAR layout and does not enable DMA export. + +Deferred BAR activation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +BAR subrange mapping cannot be programmed at bind time because the host ha= s not +assigned BAR addresses yet. Shared ``MW/DMA`` BARs therefore use a two-sta= ge +programming model: + +1. bind time: configure the BAR aperture with a temporary plain mapping +2. first host command (``CONFIGURE_MW`` or ``LINK_UP``): re-issue + ``pci_epc_set_bar()`` with the final subrange layout + +This matches the requirements for EPC subrange mapping feature. + +DMA export and ``ntb_ep_dma`` +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +When DMA export is enabled, ``pci-epf-vntb`` publishes a logical DMA locat= or in +the control block. ``ntb_hw_epf`` parses that locator during probe, reserv= es an +IRQ slice for the DMA provider, and registers the auxiliary child only aft= er +``LINK_UP`` succeeds. As a vendor-specific frontend example, ``dw-edma-aux= `` +binds to that child and exposes a DMA engine provider for the remote endpo= int +DMA instance. + +The ``ntb_ep_dma`` test client exercises that path. Both peers load the +module. Each side allocates a local test buffer and publishes the DMA addr= ess +and size through scratchpads. The responder only waits and verifies, while= the +initiator triggers one transfer with:: + + # cat /sys/kernel/debug/ntb_ep_dma/0000:01:00.0/ready + # echo 1 > /sys/kernel/debug/ntb_ep_dma/0000:01:00.0/run + # cat /sys/kernel/debug/ntb_ep_dma/0000:01:00.0/result + +The initiator side uses the remote exported DMA instance to transfer into = the +peer-published buffer. The responder verifies the contents locally and rep= orts +PASS/FAIL back through scratchpads and a doorbell. --=20 2.51.0