From nobody Tue Apr 7 14:38:27 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB4623DD510; Thu, 12 Mar 2026 16:44:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773333889; cv=none; b=iiFfkMNL4H/hTD6PMk4tVRexhxySBXLn9YS2hOjPeQeoBzg80McmDSPicDm0DNiQWDdUyRW8jQMGoMwK9Gh97L5gDsnroUP802FELJl6EwziKiT1HFJ/ijHXItnd6bjLUCU2uELFRk5wWGh5W/zdyyVsoI8Q7SngK1hZaZQPadE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773333889; c=relaxed/simple; bh=UAoFXhruskfYYT3ahUHFS27n7vA9MyWaBRf7PXqHOUU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b7hMjNNTjSGDhV7FxnTxzNrNHGhqt64Rd+ETthrjYq6vrg3TYgSdIaLLulWZAUkjdM7cPEj24/3D9/6VZpSa9NUzc9buRltxQh286arpdHwCdKB8tyvdIihKRQFCttQ2Uv5aVzCtrqmqHtol6ybvW5R1jt/iO3RMAJjyk1gF3/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Kby+tHk9; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Kby+tHk9" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2DF522C851A; Thu, 12 Mar 2026 17:44:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773333885; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=gso2J9TlFIUpfDVYlVOReC8nln0KMuVCMF3iv5VYSH4=; b=Kby+tHk9MQz/X3stk/VsVQU+Hf1p1z91yird07xVKs6oHFwO51ey+ySRSNrSa3Qs0BodP2 Uzi+B2lvtiY75HAxTKotMri4F++CnDiHVOt9+Zv8VQ0FaD/TZY2d7kl0Hxxdt6RBE7KPcj cZLEB1xxaVoaDprD5lLXb2HFWkcVJVStoo3Y6UjdzVvVVK+Bg1g5KBx8kjyK1zB2IsOd8E fFkXEF5BpLdaSz+qB2IlzdTk6xwMslEySCI6Wp/fVZO82MOKBYgAAyN+3cQl87BwtZ1RVo HGy1arNZrFGiqrzfQ0hfl4S/DEyGU9W5g+LNZDEWMbcDEmoOpFzqp4YWgdUGpg== From: Caleb James DeLisle To: linux-phy@lists.infradead.org Cc: naseefkm@gmail.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle , Krzysztof Kozlowski Subject: [PATCH 1/2] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528 Date: Thu, 12 Mar 2026 16:44:31 +0000 Message-Id: <20260312164432.569566-2-cjd@cjdns.fr> In-Reply-To: <20260312164432.569566-1-cjd@cjdns.fr> References: <20260312164432.569566-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY which behaves slightly differently because one slot is Gen1/Gen2 while the other is Gen1 only. Signed-off-by: Caleb James DeLisle Reviewed-by: Krzysztof Kozlowski --- .../phy/econet,en751221-pcie-phy.yaml | 50 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-p= cie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy= .yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml new file mode 100644 index 000000000000..987d396c1c64 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528 + +maintainers: + - Caleb James DeLisle + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen1 and + Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while + port 1 is Gen1/Gen2 capable. + +properties: + compatible: + enum: + - econet,en751221-pcie-gen1 + - econet,en751221-pcie-gen2 + - econet,en7528-pcie-gen1 + - econet,en7528-pcie-gen2 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + pcie-phy@1faf2000 { + compatible =3D "econet,en7528-pcie-gen1"; + reg =3D <0x1faf2000 0x1000>; + #phy-cells =3D <0>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 14899f1de77e..557b6a47ec98 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9120,6 +9120,12 @@ F: arch/mips/econet/ F: drivers/clocksource/timer-econet-en751221.c F: drivers/irqchip/irq-econet-en751221.c =20 +ECONET PCIE PHY DRIVER +M: Caleb James DeLisle +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml + ECRYPT FILE SYSTEM M: Tyler Hicks L: ecryptfs@vger.kernel.org --=20 2.39.5 From nobody Tue Apr 7 14:38:27 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EB0A3FA5F6; Thu, 12 Mar 2026 16:44:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773333891; cv=none; b=JXZrzWHUzadlBK1/7Zx9uETO1NoqqS1ynrqea6PuJ5olr3V1w05nThI08ctar/WLQZES85wAe3wUBjxT9elJ+d/VREVFtkRBHzibtEG3i/rSnaQ97X0keOydzzktfn99mAvbsodDL+RxF0fOYEm+rsaLanDEWhwR8SzRzXqSGjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773333891; c=relaxed/simple; bh=KEM55sR/TogjZ5VezzIFYBS9pLPjpt5yZlbGzFiX0kQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tcN5j1AC56mRxo+invFF1Jb/tZKjFaxlnB3V6oV1JE3jvnewTv6gFEikpVZ6TZVr9ou4rCcY2ICEDFrAGNhqrN9x17jLh2TyweEd4PlIALA+HNGNmy9OTEuKjPjLjtr/rIT44nXJ6o4JhV2KhBGk7L60w/ljpOWwuiMSAyevTIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=ltvfPEjX; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="ltvfPEjX" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EFF992C6C3F; Thu, 12 Mar 2026 17:44:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773333887; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=lIVo4U43vKJTmOpE3Xdpd73u3mWBksP94PzdDDxFbsc=; b=ltvfPEjXYedsVa93vCEHWNIzS8nfdV4XQBCObsn/FAP3xYtyOYePkZll1dHY/ZPk2+SbHM MJDD6kfvLyq0lZ0W1u0Ow3uqAxdY5GJ7xOhzjzJGHibmdZTu5DHiJNI4F1N7OgBG5s1k8+ 8AiwtBh3dBj53qPH57VmYpYXn8PW1ON5oCFNg/wyVPm64tJWGDGgcdsJsMHNj62TvNB/ul iK5j0g821nEKgLK3LYXl5RE84wHkz4nJpxyr4g8o9yBfFVTl8q3rfVvmYOBFL7Dmngk763 usCqUW/FEe5Hh1TfU/Z4bTH2azLR7pRCCZoMbIw/Jn1AXjCxti0RIrw1kK0JuQ== From: Caleb James DeLisle To: linux-phy@lists.infradead.org Cc: naseefkm@gmail.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle Subject: [PATCH 2/2] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs. Date: Thu, 12 Mar 2026 16:44:32 +0000 Message-Id: <20260312164432.569566-3-cjd@cjdns.fr> In-Reply-To: <20260312164432.569566-1-cjd@cjdns.fr> References: <20260312164432.569566-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Introduce support for EcoNet PCIe PHY controllers found in EN751221 and EN7528 SoCs, these SoCs are not identical but are similar, each having one Gen1 port, and one Gen1/Gen2 port. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef [cjd@cjdns.fr: add EN751221 support and refactor for clarity] Co-developed-by: Caleb James DeLisle Signed-off-by: Caleb James DeLisle --- MAINTAINERS | 1 + drivers/phy/Kconfig | 12 +++ drivers/phy/Makefile | 1 + drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++++++++++++++++++ 4 files changed, 194 insertions(+) create mode 100644 drivers/phy/phy-econet-pcie.c diff --git a/MAINTAINERS b/MAINTAINERS index 557b6a47ec98..0b2b129e168b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9125,6 +9125,7 @@ M: Caleb James DeLisle L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml +F: drivers/phy/phy-econet-pcie.c =20 ECRYPT FILE SYSTEM M: Tyler Hicks diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 02467dfd4fb0..60efc37f6eb0 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -123,6 +123,18 @@ config PHY_AIROHA_PCIE This driver create the basic PHY instance and provides initialize callback for PCIe GEN3 port. =20 +config PHY_ECONET_PCIE + tristate "EcoNet PCIe-PHY Driver" + depends on ECONET || COMPILE_TEST + depends on OF + select GENERIC_PHY + select REGMAP_MMIO + help + Say Y here to add support for EcoNet PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN1 and GEN2 ports. This PHY is found on + EcoNet SoCs including EN751221 and EN7528. + config PHY_NXP_PTN3222 tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver" depends on I2C diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index a648c2e02a83..a77f182ee8f3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) +=3D phy-pistachio-usb.o obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o +obj-$(CONFIG_PHY_ECONET_PCIE) +=3D phy-econet-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) +=3D phy-spacemit-k1-pcie.o obj-$(CONFIG_GENERIC_PHY) +=3D allwinner/ \ diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c new file mode 100644 index 000000000000..d2c6e0c1f331 --- /dev/null +++ b/drivers/phy/phy-econet-pcie.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Caleb James DeLisle + * Ahmed Naseef + */ + +#include +#include +#include +#include +#include +#include + +/* Rx detection timing for EN751221: 16*8 clock cycles */ +#define EN751221_RXDET_VAL 16 + +/* Rx detection timing when in power mode 3 */ +#define EN75_RXDET_P3_REG 0xa28 +#define EN75_RXDET_P3_MASK GENMASK(17, 9) + +/* Rx detection timing when in power mode 2 */ +#define EN75_RXDET_P2_REG 0xa2c +#define EN75_RXDET_P2_MASK GENMASK(8, 0) + +/* Rx impedance */ +#define EN75_RX_IMPEDANCE_REG 0xb2c +#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12) +enum en75_rx_impedance { + EN75_RX_IMPEDANCE_100_OHM =3D 0, + EN75_RX_IMPEDANCE_95_OHM =3D 1, + EN75_RX_IMPEDANCE_90_OHM =3D 2, +}; + +/* PLL Invert clock */ +#define EN75_PLL_PH_INV_REG 0x4a0 +#define EN75_PLL_PH_INV_MASK BIT(5) + +struct en75_phy_op { + u32 reg; + u32 mask; + u32 val; +}; + +struct en7528_pcie_phy { + struct regmap *regmap; + const struct en75_phy_op *data; +}; + +/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */ +static const struct en75_phy_op en7528_phy_gen1[] =3D { + { + .reg =3D EN75_PLL_PH_INV_REG, + .mask =3D EN75_PLL_PH_INV_MASK, + .val =3D 1, + }, + { /* sentinel */ } +}; + +/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */ +static const struct en75_phy_op en7528_phy_gen2[] =3D { + { + .reg =3D EN75_RX_IMPEDANCE_REG, + .mask =3D EN75_RX_IMPEDANCE_MASK, + .val =3D EN75_RX_IMPEDANCE_95_OHM, + }, + { /* sentinel */ } +}; + +/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */ +static const struct en75_phy_op en751221_phy_gen2[] =3D { + { + .reg =3D EN75_RXDET_P3_REG, + .mask =3D EN75_RXDET_P3_MASK, + .val =3D EN751221_RXDET_VAL, + }, + { + .reg =3D EN75_RXDET_P2_REG, + .mask =3D EN75_RXDET_P2_MASK, + .val =3D EN751221_RXDET_VAL, + }, + { /* sentinel */ } +}; + +static int en75_pcie_phy_init(struct phy *phy) +{ + struct en7528_pcie_phy *ephy =3D phy_get_drvdata(phy); + const struct en75_phy_op *data =3D ephy->data; + int i, ret; + u32 val; + + for (i =3D 0; data[i].mask || data[i].val; i++) { + if (i) + usleep_range(1000, 2000); + + val =3D field_prep(data[i].mask, data[i].val); + + ret =3D regmap_update_bits(ephy->regmap, data[i].reg, + data[i].mask, val); + if (ret) + return ret; + } + + return 0; +} + +static const struct phy_ops en75_pcie_phy_ops =3D { + .init =3D en75_pcie_phy_init, + .owner =3D THIS_MODULE, +}; + +static int en75_pcie_phy_probe(struct platform_device *pdev) +{ + struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + }; + struct device *dev =3D &pdev->dev; + const struct en75_phy_op *data; + struct phy_provider *provider; + struct en7528_pcie_phy *ephy; + void __iomem *base; + struct phy *phy; + int i; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + ephy =3D devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL); + if (!ephy) + return -ENOMEM; + + ephy->data =3D data; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* Set max_register to highest used register */ + for (i =3D 0; data[i].mask || data[i].val; i++) + if (data[i].reg > regmap_config.max_register) + regmap_config.max_register =3D data[i].reg; + + ephy->regmap =3D devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(ephy->regmap)) + return PTR_ERR(ephy->regmap); + + phy =3D devm_phy_create(dev, dev->of_node, &en75_pcie_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, ephy); + + provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id en75_pcie_phy_ids[] =3D { + { .compatible =3D "econet,en7528-pcie-gen1", .data =3D en7528_phy_gen1 }, + { .compatible =3D "econet,en7528-pcie-gen2", .data =3D en7528_phy_gen2 }, + { .compatible =3D "econet,en751221-pcie-gen1", .data =3D en7528_phy_gen1 = }, + { .compatible =3D "econet,en751221-pcie-gen2", .data =3D en751221_phy_gen= 2 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, en75_pcie_phy_ids); + +static struct platform_driver en75_pcie_phy_driver =3D { + .probe =3D en75_pcie_phy_probe, + .driver =3D { + .name =3D "econet-pcie-phy", + .of_match_table =3D en75_pcie_phy_ids, + }, +}; +module_platform_driver(en75_pcie_phy_driver); + +MODULE_AUTHOR("Caleb James DeLisle "); +MODULE_DESCRIPTION("EcoNet PCIe PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5