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Thu, 12 Mar 2026 09:04:29 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/2] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add PHY interrupt support Date: Thu, 12 Mar 2026 16:04:06 +0000 Message-ID: <20260312160407.3387840-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260312160407.3387840-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260312160407.3387840-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add interrupt support for the GMAC1 and GMAC2 PHYs on the RZ/N2H EVK board. The PHYs are connected to the ICU via IRQ14 and IRQ15 lines respectively. Define RZN2H_IRQxx macros in the SoC DTSI to map the ICU IRQ_NS lines to their absolute ICU interrupt space offsets. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 18 ++++++++++++++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 9 +++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 6218cef2fca5..f697e9698ed3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -8,6 +8,24 @@ #include #include =20 +/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ +#define RZN2H_IRQ0 16 +#define RZN2H_IRQ1 17 +#define RZN2H_IRQ2 18 +#define RZN2H_IRQ3 19 +#define RZN2H_IRQ4 20 +#define RZN2H_IRQ5 21 +#define RZN2H_IRQ6 22 +#define RZN2H_IRQ7 23 +#define RZN2H_IRQ8 24 +#define RZN2H_IRQ9 25 +#define RZN2H_IRQ10 26 +#define RZN2H_IRQ11 27 +#define RZN2H_IRQ12 28 +#define RZN2H_IRQ13 29 +#define RZN2H_IRQ14 30 +#define RZN2H_IRQ15 31 + / { compatible =3D "renesas,r9a09g087"; #address-cells =3D <2>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 19f0a2c06753..821a74edab50 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -303,6 +303,7 @@ &i2c1 { }; =20 &mdio1_phy { + interrupts-extended =3D <&icu RZN2H_IRQ15 IRQ_TYPE_EDGE_FALLING>; /* * PHY3 Reset Configuration: * @@ -312,6 +313,7 @@ &mdio1_phy { }; =20 &mdio2_phy { + interrupts-extended =3D <&icu RZN2H_IRQ14 IRQ_TYPE_EDGE_FALLING>; /* * PHY2 Reset Configuration: * @@ -338,6 +340,7 @@ can1_pins: can1-pins { * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, * P31_2, P31_4 and P31_5 are used for Ethernet port 2 + * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14 */ gmac2_pins: gmac2-pins { pinmux =3D , /* ETH2_TXCLK */ @@ -358,7 +361,8 @@ gmac2_pins: gmac2-pins { , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ - ; 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charset="utf-8" From: Lad Prabhakar Add interrupt support for the GMAC1 and GMAC2 PHYs on the RZ/T2H EVK board. The PHYs are connected to the ICU via IRQ3 and IRQ13 lines respectively. Define RZT2H_IRQxx macros in the SoC DTSI to map the ICU IRQ_NS lines to their absolute ICU interrupt space offsets. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 18 ++++++++++++++++++ .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 8 ++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 81f6a36e6e72..3761551c9647 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -8,6 +8,24 @@ #include #include =20 +/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ +#define RZT2H_IRQ0 16 +#define RZT2H_IRQ1 17 +#define RZT2H_IRQ2 18 +#define RZT2H_IRQ3 19 +#define RZT2H_IRQ4 20 +#define RZT2H_IRQ5 21 +#define RZT2H_IRQ6 22 +#define RZT2H_IRQ7 23 +#define RZT2H_IRQ8 24 +#define RZT2H_IRQ9 25 +#define RZT2H_IRQ10 26 +#define RZT2H_IRQ11 27 +#define RZT2H_IRQ12 28 +#define RZT2H_IRQ13 29 +#define RZT2H_IRQ14 30 +#define RZT2H_IRQ15 31 + / { compatible =3D "renesas,r9a09g077"; #address-cells =3D <2>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index e9639bbb2d70..9d9ad9261781 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -224,10 +224,12 @@ &i2c1 { }; =20 &mdio1_phy { + interrupts-extended =3D <&icu RZT2H_IRQ3 IRQ_TYPE_EDGE_FALLING>; reset-gpios =3D <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; }; =20 &mdio2_phy { + interrupts-extended =3D <&icu RZT2H_IRQ13 IRQ_TYPE_EDGE_FALLING>; /* * PHY2 Reset Configuration: * @@ -274,7 +276,8 @@ gmac2_pins: gmac2-pins { , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ - ; /* ETH2_REFCLK */ + , /* ETH2_REFCLK */ + ; /* IRQ13 */ }; =20 /* @@ -302,7 +305,8 @@ gmac1_pins: gmac1-pins { , /* ETH3_COL */ , /* GMAC1_MDC */ , /* GMAC1_MDIO */ - ; /* ETH3_REFCLK */ + , /* ETH3_REFCLK */ + ; /* IRQ3 */ }; =20 /* --=20 2.53.0