From nobody Tue Apr 7 18:01:52 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A054D3939D0; Thu, 12 Mar 2026 11:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773315218; cv=none; b=TylN/jdv+FXSe+WBoFi4S7q29uKKiSgx23qVPxgzRJ+DXu60G9WZTnSrC/5nk+SNIY111XRE256DQd7dDP3xOa7yQiugBcKxqgiyRahdG3Bf8maqZH0Id5/WqksV9chsf/bMkR1PlWE7MOI0De3w5HEPjRK00EQ6eEe9G3/Fpuo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773315218; c=relaxed/simple; bh=a+WHMjiTNRDIjVuQ9+Q0qVRVa1tCplNh22auIHPRdaE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eIaE9nh3iVCypCf8+eJLnJyqg64cY1coo9BiJVHYvWezO2BwYh2yuGLuiVsueKrQtqqGcRR2TVC5gPBzUiDGglT7JudLtw0jNYmzRMaLvzLpTT1GGHXynueuVpM/i22b84+4ffwuz8vlsiVeVKvzjTHbRW5j6lB5x1A5c6OaAGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=VSzbmUkm; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="VSzbmUkm" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 62CBUevxE2456770, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1773315041; bh=J7IFS+Nq88jf8GKKNBe7mAAapyjw4fDD+dL+TVSwaL0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=VSzbmUkm0aF8/l06bUGmL+bA5BzD1OzXoo+8necBJrjxEVvMYJdDgDeOn1x/tc1Oy +H4PGxCa/fjz43KEPkOHsX8IxDllYPrm478hPoWf8l9rs9WO/RF2OeNzeJJeDPz7y4 sYKvqEAmyBCtIcrAihNc8DwNBTCtyoF53mSF6G1VnS6RFeNtxqg3IJGaKoIwbwWC/v pArqJFHrFuRs7iFBMyXJmxpYgbi1RRG3a1nv4Brnu/jmI0obCs5S5pMv2gcH7KjCOl AeVA0M9g6vzlnaePtDMI5I4vuRh5woA8HNVePSCfj+x99MaZoxnJ3JrP0F1SAOMjDh FIvwS3EumkORA== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 62CBUevxE2456770 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 12 Mar 2026 19:30:40 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 12 Mar 2026 19:30:40 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 12 Mar 2026 19:30:40 +0800 From: Yu-Chun Lin To: , , , , CC: , , , , , , , , , , Subject: [PATCH v3 1/7] dt-bindings: pincfg-node: Add input-voltage-microvolt property Date: Thu, 12 Mar 2026 19:30:34 +0800 Message-ID: <20260312113040.68189-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260312113040.68189-1-eleanor.lin@realtek.com> References: <20260312113040.68189-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add a generic pin configuration property "input-voltage-microvolt" to support hardware designs where the input logic threshold is decoupled from the power supply voltage. This property allows the pinctrl driver to configure the correct internal reference voltage for pins that need to accept input signals at a different voltage level than their power supply. For example, a pin powered by 3.3V may need to accept 1.8V logic signals. This defines the reference for VIH (Input High Voltage) and VIL (Input Low Voltage) thresholds, enabling proper signal detection across different voltage domains. Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v3: - Rebased onto the devel branch of the pinctrl tree. - Improved commit message and description. --- Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/D= ocumentation/devicetree/bindings/pinctrl/pincfg-node.yaml index fe936ab09104..fd49a0d53bf0 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -162,6 +162,11 @@ properties: this affects the expected delay in ps before latching a value to an output pin. =20 + input-voltage-microvolt: + description: Specifies the input voltage level of the pin in microvolt= s. + This defines the reference for VIH (Input High Voltage) and VIL + (Input Low Voltage) thresholds for proper signal detection. + allOf: - if: required: --=20 2.34.1