From nobody Tue Apr 7 18:16:18 2026 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C1FC3BED54 for ; Thu, 12 Mar 2026 11:24:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314695; cv=none; b=VrHsA+BQ+7Yo9ZZYzVq2aY5FecvLf+Ko7Idy9ZbmMxP60PQ161N09LpKR1XFkfH+d+26D/SDSMsghzuvM8ZqHJ86cDLnoJskWEAk/d4SK2PRm4b48kTRYTt/Jn4kwun1LP5xomwUgRpGVWliGCGP8MEeGm2jmIRYDUZ2WP47KeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314695; c=relaxed/simple; bh=SHsUWsOET7NnIcPa0jYYlqLqNbSur5ziIMfCgbWbCrM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fVIW+FHxPl/S968avx+iFbwap2f6lEJV89W9Gtv8DZPNv46uEs91N3440GvpqsWoKoDR8GZp1NvxxxSY/KJWnu3hFpi5gJXauYGt2fGTRSnvaiGYATDuPTY1bJ4kTrPysNL3Q9SOXT5zHHvEBOPShjcilvYfGst0NdZHgPQnZ7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=oILVuSdh; arc=none smtp.client-ip=95.215.58.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="oILVuSdh" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oLUzWeEcNPzK2JN8Mrg4INR+pFs0gxDSLlWR+/wJ15k=; b=oILVuSdhrgvJcsjqzi4KE/t0d6Jm7LKOudVqwAu8zyIf3a2VLHUpesausSf7eyYyA324SV F3uGERqDjBOYunaYWk3fOOSg0XGqoRFCDPGgMpZzEGjRu2c3c8D/ju6Ubw6OIcpHEZi0S2 haNsyPJGyOsEIHUlTJhcK5fMnvmPlFn8mcS3jdIn5NJWZoHWyEswALXBtteeExg/LIHXuC AbzzOfRyUug48xTtfJL3iK40b5DrtYfNftvLtZj9RjsRhjqsqCcvtnWS0i+/eUTazPwwA5 jNdkPOIM4Y3JiP0gOSpBXmoRvN5zPy6PzDhw0/qWzCN+ud5EmIKdgeMb7Npjuw== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/11] clk: qcom: camcc-sc8180x: Refactor to use qcom_cc_driver_data Date: Thu, 12 Mar 2026 08:12:16 -0300 Message-ID: <20260312112321.370983-12-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Use a qcom_cc_driver_data struct instead of a long custom probe callback to align with modern qcom/gcc-*.c style. No functional change intended. Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/camcc-sc8180x.c | 67 +++++++++++++++----------------- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8180x.c b/drivers/clk/qcom/camcc-sc81= 80x.c index 67b2055bd212..bbd7add69cb0 100644 --- a/drivers/clk/qcom/camcc-sc8180x.c +++ b/drivers/clk/qcom/camcc-sc8180x.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -63,6 +62,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -138,6 +138,7 @@ static const struct alpha_pll_config cam_cc_pll1_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -167,6 +168,7 @@ static const struct alpha_pll_config cam_cc_pll2_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D regera_vco, .num_vco =3D ARRAY_SIZE(regera_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA], @@ -219,6 +221,7 @@ static const struct alpha_pll_config cam_cc_pll3_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -248,6 +251,7 @@ static const struct alpha_pll_config cam_cc_pll4_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -277,6 +281,7 @@ static const struct alpha_pll_config cam_cc_pll5_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x4078, + .config =3D &cam_cc_pll5_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -306,6 +311,7 @@ static const struct alpha_pll_config cam_cc_pll6_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x40f0, + .config =3D &cam_cc_pll6_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -2810,6 +2816,21 @@ static const struct qcom_reset_map cam_cc_sc8180x_re= sets[] =3D { [CAM_CC_MCLK7_BCR] =3D { 0x50e0 }, }; =20 +static struct clk_alpha_pll *cam_cc_sc8180x_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, +}; + +static u32 cam_cc_sc8180x_critical_cbcrs[] =3D { + 0xc1e4, /* CAM_CC_GDSC_CLK */ + 0xc200, /* CAM_CC_SLEEP_CLK */ +}; + static const struct regmap_config cam_cc_sc8180x_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2818,6 +2839,13 @@ static const struct regmap_config cam_cc_sc8180x_reg= map_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data cam_cc_sc8180x_driver_data =3D { + .alpha_plls =3D cam_cc_sc8180x_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sc8180x_plls), + .clk_cbcrs =3D cam_cc_sc8180x_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sc8180x_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sc8180x_desc =3D { .config =3D &cam_cc_sc8180x_regmap_config, .clks =3D cam_cc_sc8180x_clocks, @@ -2826,6 +2854,8 @@ static const struct qcom_cc_desc cam_cc_sc8180x_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sc8180x_resets), .gdscs =3D cam_cc_sc8180x_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sc8180x_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sc8180x_driver_data, }; =20 static const struct of_device_id cam_cc_sc8180x_match_table[] =3D { @@ -2836,40 +2866,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sc8180x_match_table); =20 static int cam_cc_sc8180x_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sc8180x_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_trion_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_trion_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0xc200); /* CAM_CC_SLEEP_CLK */ - - ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sc8180x_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; + return qcom_cc_probe(pdev, &cam_cc_sc8180x_desc); } =20 static struct platform_driver cam_cc_sc8180x_driver =3D { --=20 2.52.0