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Thu, 12 Mar 2026 01:27:14 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Lad Prabhakar , Wolfram Sang , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH 2/2] serial: sh-sci: Add support for RZ/G3L RSCI Date: Thu, 12 Mar 2026 08:26:59 +0000 Message-ID: <20260312082708.98835-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260312082708.98835-1-biju.das.jz@bp.renesas.com> References: <20260312082708.98835-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for RZ/G3L RSCI. The RSCI IP found on the RZ/G3L SoC is similar to RZ/G3E, but it has 3 clocks (2 module clocks + 1 external clock) instead of 6 clocks (5 module clocks + 1 external clock) on the RZ/G3E. Both RZ/G3L and RZ/G3E have a 32-bit FIFO, but RZ/G3L has a single TCLK with internal dividers, whereas the RZ/G3E has explicit clocks for TCLK and its dividers. Add a new port type RSCI_PORT_SCIF32_SINGLE_TCLK to handle this clock difference. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/tty/serial/rsci.c | 13 +++++++++++++ drivers/tty/serial/rsci.h | 1 + drivers/tty/serial/sh-sci-common.h | 1 + drivers/tty/serial/sh-sci.c | 14 +++++++++++--- 4 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index c3f12df693ad..b00c9e385169 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -695,6 +695,13 @@ struct sci_of_data of_rsci_rzg3e_data =3D { .params =3D &rsci_rzg3e_port_params, }; =20 +struct sci_of_data of_rsci_rzg3l_data =3D { + .type =3D RSCI_PORT_SCIF32_SINGLE_TCLK, + .ops =3D &rsci_port_ops, + .uart_ops =3D &rsci_uart_ops, + .params =3D &rsci_rzg3e_port_params, +}; + struct sci_of_data of_rsci_rzt2h_data =3D { .type =3D RSCI_PORT_SCIF16, .ops =3D &rsci_port_ops, @@ -703,6 +710,11 @@ struct sci_of_data of_rsci_rzt2h_data =3D { }; =20 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON +static int __init rsci_rzg3l_early_console_setup(struct earlycon_device *d= evice, + const char *opt) +{ + return scix_early_console_setup(device, &of_rsci_rzg3l_data); +} =20 static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *d= evice, const char *opt) @@ -716,6 +728,7 @@ static int __init rsci_rzt2h_early_console_setup(struct= earlycon_device *device, return scix_early_console_setup(device, &of_rsci_rzt2h_data); } =20 +OF_EARLYCON_DECLARE(rsci, "renesas,r9a08g046-rsci", rsci_rzg3l_early_conso= le_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_conso= le_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_conso= le_setup); =20 diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h index 2aa2ba3973ee..0985fd1b3348 100644 --- a/drivers/tty/serial/rsci.h +++ b/drivers/tty/serial/rsci.h @@ -6,6 +6,7 @@ #include "sh-sci-common.h" =20 extern struct sci_of_data of_rsci_rzg3e_data; +extern struct sci_of_data of_rsci_rzg3l_data; extern struct sci_of_data of_rsci_rzt2h_data; =20 #endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index f363a659c46a..01ff9fced803 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -9,6 +9,7 @@ enum SCI_PORT_TYPE { RSCI_PORT_SCIF16 =3D BIT(7) | 0, RSCI_PORT_SCIF32 =3D BIT(7) | 1, + RSCI_PORT_SCIF32_SINGLE_TCLK =3D BIT(7) | 2, }; =20 enum SCI_CLKS { diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index bd7486315338..6c819b6b2425 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1184,7 +1184,8 @@ static int sci_handle_errors(struct uart_port *port) =20 static bool sci_is_rsci_type(u8 type) { - return (type =3D=3D RSCI_PORT_SCIF16 || type =3D=3D RSCI_PORT_SCIF32); + return (type =3D=3D RSCI_PORT_SCIF16 || type =3D=3D RSCI_PORT_SCIF32 || + type =3D=3D RSCI_PORT_SCIF32_SINGLE_TCLK); } =20 static int sci_handle_fifo_overrun(struct uart_port *port) @@ -3181,7 +3182,8 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) =20 if (sci_port->type =3D=3D PORT_HSCIF) { clk_names[SCI_SCK] =3D "hsck"; - } else if (sci_port->type =3D=3D RSCI_PORT_SCIF16) { + } else if (sci_port->type =3D=3D RSCI_PORT_SCIF16 || + sci_port->type =3D=3D RSCI_PORT_SCIF32_SINGLE_TCLK) { clk_names[SCI_FCK] =3D "operation"; clk_names[SCI_BRG_INT] =3D "bus"; } else if (sci_port->type =3D=3D RSCI_PORT_SCIF32) { @@ -3196,7 +3198,8 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) if (IS_ERR(clk)) return PTR_ERR(clk); =20 - if (!clk && sci_port->type =3D=3D RSCI_PORT_SCIF16 && + if (!clk && (sci_port->type =3D=3D RSCI_PORT_SCIF16 || + sci_port->type =3D=3D RSCI_PORT_SCIF32_SINGLE_TCLK) && (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); =20 @@ -3330,6 +3333,7 @@ static int sci_init_single(struct platform_device *de= v, break; case PORT_SCIFA: case RSCI_PORT_SCIF32: + case RSCI_PORT_SCIF32_SINGLE_TCLK: sci_port->rx_trigger =3D 32; break; case PORT_SCIF: @@ -3663,6 +3667,10 @@ static const struct of_device_id of_sci_match[] __ma= ybe_unused =3D { .data =3D &of_sci_scif_rzv2h, }, #ifdef CONFIG_SERIAL_RSCI + { + .compatible =3D "renesas,r9a08g046-rsci", + .data =3D &of_rsci_rzg3l_data, + }, { .compatible =3D "renesas,r9a09g047-rsci", .data =3D &of_rsci_rzg3e_data, --=20 2.43.0