From nobody Thu Apr 2 09:30:24 2026 Received: from canpmsgout11.his.huawei.com (canpmsgout11.his.huawei.com [113.46.200.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 473C63B2FF2 for ; Thu, 12 Mar 2026 07:50:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773301839; cv=none; b=a2HGc4aX2dUDdSWDR7JBwchD9cfYdO5Uoo5ckCMI9ugorcpDSS7CD0MfECwPVWUnMSKJm/E4JRHemBIbO1oWLl+AZzw40jJcWSph+BYwoWJjr3AWGAmn+BX7PRvNnmm3LQOouJ1AA/lLfCzYkS34utnF6b1yM2TyCEzh78sRM8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773301839; c=relaxed/simple; bh=KOev56awIibPit81pQ2HcThaggfDHcHX9KW0NB/bmkY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I2aWy6cPynL4GfJX6sgT8BMTmU6O10V1Ac4S43w7659Iaw+IS/Un/5BXF0o46KbyoVWkym8n7wZ007AZZBeaGv5JDfWVLpd4GVITyn1QAIY/qSJJYecJdkwXQU5JZeAfe1zUxF0mbWP2jN5HHz6FZEpuyfdLuvygv49hyRS0uec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=rgy6Xa8W; arc=none smtp.client-ip=113.46.200.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="rgy6Xa8W" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=ZqnUpMmvb2aO78vdRlatU7bqodMyYJRbbmJxgherU+k=; b=rgy6Xa8Wr9JaDAQXc58EVX7hmrJ6df9+lQuBHhuQks8AV7fg3ytYE1FLoQzVK2y81JDScybSO djBzu/xJXv49Xs9pgUBxO8fR1kqgjx6EppxkFkeH+UIwxVVcQo4Y70kQqag8F3zWNRSbVZzCbyz yIOxdWmlrUbfL7+mcp0rkrU= Received: from mail.maildlp.com (unknown [172.19.163.127]) by canpmsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4fWfmf4KyPzKm73; Thu, 12 Mar 2026 15:45:38 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 2303340571; Thu, 12 Mar 2026 15:50:35 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 12 Mar 2026 15:50:32 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 12 Mar 2026 15:50:32 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH RESEND drm-dp 1/4] drm/hisilicon/hibmc: add updating link cap in DP detect() Date: Thu, 12 Mar 2026 15:41:59 +0800 Message-ID: <20260312074202.1491504-2-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260312074202.1491504-1-shiyongbang@huawei.com> References: <20260312074202.1491504-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He In the past, the link cap is updated in link training at encoder enable stage, but the hibmc_dp_mode_valid() is called before it, which will use DP link's rate and lanes. So add the hibmc_dp_update_caps() in hibmc_dp_update_caps() to avoid some potential risks. Fixes: e6c7c59da494 ("drm/hisilicon/hibmc: add dp mode valid check") Signed-off-by: Lin He Signed-off-by: Yongbang Shi Reviewed-by: Tao Tian --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 1 + drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 2 +- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index f9ee7ebfec55..f53dac256ee0 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -69,5 +69,6 @@ int hibmc_dp_link_training(struct hibmc_dp_dev *dp); int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp); int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp); int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC= _DP_LANE_NUM_MAX]); +void hibmc_dp_update_caps(struct hibmc_dp_dev *dp); =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c index 0726cb5b736e..8c53f16db516 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -325,7 +325,7 @@ static int hibmc_dp_link_downgrade_training_eq(struct h= ibmc_dp_dev *dp) return hibmc_dp_link_reduce_rate(dp); } =20 -static void hibmc_dp_update_caps(struct hibmc_dp_dev *dp) +void hibmc_dp_update_caps(struct hibmc_dp_dev *dp) { dp->link.cap.link_rate =3D dp->dpcd[DP_MAX_LINK_RATE]; if (dp->link.cap.link_rate > DP_LINK_BW_8_1 || !dp->link.cap.link_rate) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index 616821e3c933..35dff7bfbf76 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -41,6 +41,8 @@ static bool hibmc_dp_get_dpcd(struct hibmc_dp_dev *dp_dev) if (ret) return false; =20 + hibmc_dp_update_caps(dp_dev); + dp_dev->is_branch =3D drm_dp_is_branch(dp_dev->dpcd); =20 ret =3D drm_dp_read_desc(dp_dev->aux, &dp_dev->desc, dp_dev->is_branch); --=20 2.33.0 From nobody Thu Apr 2 09:30:24 2026 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3DEE3ACEEE for ; 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Thu, 12 Mar 2026 15:50:32 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH RESEND drm-dp 2/4] drm/hisilicon/hibmc: fix no showing when no connectors connected Date: Thu, 12 Mar 2026 15:42:00 +0800 Message-ID: <20260312074202.1491504-3-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260312074202.1491504-1-shiyongbang@huawei.com> References: <20260312074202.1491504-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He Our chip support KVM over IP feature, so hibmc driver need to support displaying without any connectors plugged in. If no connectors are connected, the vdac connector status should be set to 'connected' to ensure proper KVM display functionality. Additionally, for previous-generation products that may lack hardware link support and thus cannot detect the monitor, the same approach should be applied to ensure VGA display functionality. Add phys_state in the struct of dp and vdac to check all physical outputs. For get_modes: using BMC modes for connector if no display is attached to phys VGA cable, otherwise use EDID modes by drm_connector_helper_get_modes, because KVM doesn't provide EDID reads. Fixes: 4c962bc929f1 ("drm/hisilicon/hibmc: Add vga connector detect functio= ns") Reported-by: Thomas Zimmermann Closes: https://lore.kernel.org/all/0eb5c509-2724-4c57-87ad-74e4270d5a5a@su= se.de/ Signed-off-by: Lin He Signed-off-by: Yongbang Shi Reviewed-by: Tao Tian --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 1 + .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 33 ++++++++---- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 1 + .../gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 52 ++++++++++++------- 4 files changed, 59 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 31316fe1ea8d..dfaeabd05d46 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -55,6 +55,7 @@ struct hibmc_dp { struct drm_dp_aux aux; struct hibmc_dp_cbar_cfg cfg; u32 irq_status; + int phys_state; }; =20 int hibmc_dp_hw_init(struct hibmc_dp *dp); diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index 35dff7bfbf76..8fe2eb51a0b3 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -61,27 +61,38 @@ static int hibmc_dp_detect(struct drm_connector *connec= tor, { struct hibmc_dp *dp =3D to_hibmc_dp(connector); struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; - int ret; + int ret =3D connector_status_disconnected; =20 if (dp->irq_status) { - if (dp_dev->hpd_status !=3D HIBMC_HPD_IN) - return connector_status_disconnected; + if (dp_dev->hpd_status !=3D HIBMC_HPD_IN) { + ret =3D connector_status_disconnected; + goto exit; + } } =20 - if (!hibmc_dp_get_dpcd(dp_dev)) - return connector_status_disconnected; + if (!hibmc_dp_get_dpcd(dp_dev)) { + ret =3D connector_status_disconnected; + goto exit; + } =20 - if (!dp_dev->is_branch) - return connector_status_connected; + if (!dp_dev->is_branch) { + ret =3D connector_status_connected; + goto exit; + } =20 if (drm_dp_read_sink_count_cap(connector, dp_dev->dpcd, &dp_dev->desc) && dp_dev->downstream_ports[0] & DP_DS_PORT_HPD) { ret =3D drm_dp_read_sink_count(dp_dev->aux); - if (ret > 0) - return connector_status_connected; + if (ret > 0) { + ret =3D connector_status_connected; + goto exit; + } } =20 - return connector_status_disconnected; +exit: + dp->phys_state =3D ret; + + return ret; } =20 static int hibmc_dp_mode_valid(struct drm_connector *connector, @@ -243,5 +254,7 @@ int hibmc_dp_init(struct hibmc_drm_private *priv) =20 connector->polled =3D DRM_CONNECTOR_POLL_HPD; =20 + dp->phys_state =3D connector_status_disconnected; + return 0; } diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.h index ca8502e2760c..6abb49b5107b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h @@ -31,6 +31,7 @@ struct hibmc_vdac { struct drm_connector connector; struct i2c_adapter adapter; struct i2c_algo_bit_data bit_data; + int phys_state; }; =20 struct hibmc_drm_private { diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c b/drivers/gpu= /drm/hisilicon/hibmc/hibmc_drm_vdac.c index 841e81f47b68..502494cba541 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c @@ -25,27 +25,19 @@ static int hibmc_connector_get_modes(struct drm_connector *connector) { struct hibmc_vdac *vdac =3D to_hibmc_vdac(connector); - const struct drm_edid *drm_edid; - int count; + int count =3D 0; =20 - drm_edid =3D drm_edid_read_ddc(connector, &vdac->adapter); + if (vdac->phys_state =3D=3D connector_status_connected) + count =3D drm_connector_helper_get_modes(connector); =20 - drm_edid_connector_update(connector, drm_edid); - - if (drm_edid) { - count =3D drm_edid_connector_add_modes(connector); - if (count) - goto out; + if (count <=3D 0) { + drm_edid_connector_update(connector, NULL); + count =3D drm_add_modes_noedid(connector, + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); + drm_set_preferred_mode(connector, 1024, 768); } =20 - count =3D drm_add_modes_noedid(connector, - connector->dev->mode_config.max_width, - connector->dev->mode_config.max_height); - drm_set_preferred_mode(connector, 1024, 768); - -out: - drm_edid_free(drm_edid); - return count; } =20 @@ -57,10 +49,32 @@ static void hibmc_connector_destroy(struct drm_connecto= r *connector) drm_connector_cleanup(connector); } =20 +static int hibmc_vdac_detect(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, + bool force) +{ + struct hibmc_drm_private *priv =3D to_hibmc_drm_private(connector->dev); + struct hibmc_vdac *vdac =3D to_hibmc_vdac(connector); + + vdac->phys_state =3D drm_connector_helper_detect_from_ddc(connector, + ctx, force); + + /* If the DP connectors are disconnected, the hibmc_vdac_detect function + * must return a connected state to ensure KVM display functionality. + * Additionally, for previous-generation products that may lack hardware + * link support and thus cannot detect the monitor, hibmc_vdac_detect + * should also return a connected state. + */ + if (priv->dp.phys_state !=3D connector_status_connected) + return connector_status_connected; + + return vdac->phys_state; +} + static const struct drm_connector_helper_funcs hibmc_connector_helper_funcs =3D { .get_modes =3D hibmc_connector_get_modes, - .detect_ctx =3D drm_connector_helper_detect_from_ddc, + .detect_ctx =3D hibmc_vdac_detect, }; =20 static const struct drm_connector_funcs hibmc_connector_funcs =3D { @@ -130,6 +144,8 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv) =20 connector->polled =3D DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DIS= CONNECT; =20 + vdac->phys_state =3D connector_status_connected; + return 0; =20 err: --=20 2.33.0 From nobody Thu Apr 2 09:30:24 2026 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A701E3B2FED for ; Thu, 12 Mar 2026 07:50:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773301839; cv=none; b=L7EcXXWL17l+Ubprttz/K10zxmw7QSWhEi2/1vlcR3wQ+I1TGNkNXqjSMea1idxS2eDL+KAqvgpSXNOeEoLftHwESTBgYyPo4pcaJBkv3gfSfOD+RGUPFdyzS8HbZbi7yrStKtuR7mB1Hel4AKKITrGyma0DPh/4ayvaAXPHfvs= ARC-Message-Signature: i=1; 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Thu, 12 Mar 2026 15:50:33 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH RESEND drm-dp 3/4] drm/hisilicon/hibmc: move display contrl config to hibmc_probe() Date: Thu, 12 Mar 2026 15:42:01 +0800 Message-ID: <20260312074202.1491504-4-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260312074202.1491504-1-shiyongbang@huawei.com> References: <20260312074202.1491504-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He If there's no VGA output, this encoder modeset won't be called, which will cause displaying data from GPU being cut off. It's actually a common display config for DP and VGA, so move the vdac encoder modeset to driver load stage. Fixes: 5294967f4ae4 ("drm/hisilicon/hibmc: Add support for VDAC") Signed-off-by: Lin He Signed-off-by: Yongbang Shi Reviewed-by: Tao Tian --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 14 ++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 22 ------------------- 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index 289304500ab0..c7ce44a5370b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -214,6 +214,18 @@ void hibmc_set_current_gate(struct hibmc_drm_private *= priv, unsigned int gate) writel(gate, mmio + gate_reg); } =20 +static void hibmc_display_ctrl(struct hibmc_drm_private *priv) +{ + u32 reg; + + reg =3D readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); + reg |=3D HIBMC_DISPLAY_CONTROL_FPVDDEN(1); + reg |=3D HIBMC_DISPLAY_CONTROL_PANELDATE(1); + reg |=3D HIBMC_DISPLAY_CONTROL_FPEN(1); + reg |=3D HIBMC_DISPLAY_CONTROL_VBIASEN(1); + writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); +} + static void hibmc_hw_config(struct hibmc_drm_private *priv) { u32 reg; @@ -245,6 +257,8 @@ static void hibmc_hw_config(struct hibmc_drm_private *p= riv) reg |=3D HIBMC_MSCCTL_LOCALMEM_RESET(1); =20 writel(reg, priv->mmio + HIBMC_MISC_CTRL); + + hibmc_display_ctrl(priv); } =20 static int hibmc_hw_map(struct hibmc_drm_private *priv) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c b/drivers/gpu= /drm/hisilicon/hibmc/hibmc_drm_vdac.c index 502494cba541..b02e9753112b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c @@ -85,26 +85,6 @@ static const struct drm_connector_funcs hibmc_connector_= funcs =3D { .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, }; =20 -static void hibmc_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - u32 reg; - struct drm_device *dev =3D encoder->dev; - struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dev); - - reg =3D readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); - reg |=3D HIBMC_DISPLAY_CONTROL_FPVDDEN(1); - reg |=3D HIBMC_DISPLAY_CONTROL_PANELDATE(1); - reg |=3D HIBMC_DISPLAY_CONTROL_FPEN(1); - reg |=3D HIBMC_DISPLAY_CONTROL_VBIASEN(1); - writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); -} - -static const struct drm_encoder_helper_funcs hibmc_encoder_helper_funcs = =3D { - .mode_set =3D hibmc_encoder_mode_set, -}; - int hibmc_vdac_init(struct hibmc_drm_private *priv) { struct drm_device *dev =3D &priv->dev; @@ -127,8 +107,6 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv) goto err; } =20 - drm_encoder_helper_add(encoder, &hibmc_encoder_helper_funcs); - ret =3D drm_connector_init_with_ddc(dev, connector, &hibmc_connector_funcs, DRM_MODE_CONNECTOR_VGA, --=20 2.33.0 From nobody Thu Apr 2 09:30:24 2026 Received: from canpmsgout05.his.huawei.com (canpmsgout05.his.huawei.com [113.46.200.220]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D99C53B2FF6 for ; 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Thu, 12 Mar 2026 15:50:34 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 12 Mar 2026 15:50:33 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH RESEND drm-dp 4/4] drm/hisilicon/hibmc: use clock to look up the PLL value Date: Thu, 12 Mar 2026 15:42:02 +0800 Message-ID: <20260312074202.1491504-5-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260312074202.1491504-1-shiyongbang@huawei.com> References: <20260312074202.1491504-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He In the past, we use width and height to look up our PLL value. But actually the actual clock check is also necessnary. There are some resolutions that width and height same, but its clock different. Add the clock check when using pll_table to determine the PLL value. Fixes: da52605eea8f ("drm/hisilicon/hibmc: Add support for display engine") Signed-off-by: Lin He Signed-off-by: Yongbang Shi Reviewed-by: Tao Tian --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 80 +++++++++++-------- 1 file changed, 46 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_de.c index 89bed78f1466..8561acbbc3c8 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -22,6 +22,8 @@ #include "hibmc_drm_drv.h" #include "hibmc_drm_regs.h" =20 +#define CLOCK_TOLERANCE 100 /* kHz tolerance */ + struct hibmc_display_panel_pll { u64 M; u64 N; @@ -32,26 +34,43 @@ struct hibmc_display_panel_pll { struct hibmc_dislay_pll_config { u64 hdisplay; u64 vdisplay; + int clock; u32 pll1_config_value; u32 pll2_config_value; }; =20 static const struct hibmc_dislay_pll_config hibmc_pll_table[] =3D { - {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, - {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, - {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, - {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, - {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, - {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, - {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, - {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, - {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, - {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, - {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, - {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, - {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, + {640, 480, 25000, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, + {800, 600, 40000, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, + {1024, 768, 65000, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, + {1152, 864, 78750, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, + {1280, 768, 80000, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, + {1280, 720, 74375, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, + {1280, 960, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1280, 1024, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1440, 900, 105952, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, + {1600, 900, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1600, 1200, 162500, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, + {1920, 1080, 148750, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, + {1920, 1200, 193750, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, }; =20 +static int hibmc_get_best_clock_idx(const struct drm_display_mode *mode) +{ + int i, diff; + + for (i =3D 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { + if (hibmc_pll_table[i].hdisplay =3D=3D mode->hdisplay && + hibmc_pll_table[i].vdisplay =3D=3D mode->vdisplay) { + diff =3D abs(mode->clock - hibmc_pll_table[i].clock); + if (diff < mode->clock / 100) /* tolerance 1/100 */ + return i; + } + } + + return -EOPNOTSUPP; +} + static int hibmc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -214,17 +233,13 @@ static enum drm_mode_status hibmc_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { - size_t i =3D 0; int vrefresh =3D drm_mode_vrefresh(mode); =20 if (vrefresh < 59 || vrefresh > 61) return MODE_NOCLOCK; =20 - for (i =3D 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { - if (hibmc_pll_table[i].hdisplay =3D=3D mode->hdisplay && - hibmc_pll_table[i].vdisplay =3D=3D mode->vdisplay) - return MODE_OK; - } + if (hibmc_get_best_clock_idx(mode) >=3D 0) + return MODE_OK; =20 return MODE_BAD; } @@ -281,23 +296,20 @@ static void set_vclock_hisilicon(struct drm_device *d= ev, u64 pll) writel(val, priv->mmio + CRT_PLL1_HS); } =20 -static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) +static void get_pll_config(struct drm_display_mode *mode, u32 *pll1, u32 *= pll2) { - size_t i; - size_t count =3D ARRAY_SIZE(hibmc_pll_table); - - for (i =3D 0; i < count; i++) { - if (hibmc_pll_table[i].hdisplay =3D=3D x && - hibmc_pll_table[i].vdisplay =3D=3D y) { - *pll1 =3D hibmc_pll_table[i].pll1_config_value; - *pll2 =3D hibmc_pll_table[i].pll2_config_value; - return; - } + int idx; + + idx =3D hibmc_get_best_clock_idx(mode); + if (idx < 0) { + /* if found none, we use default value */ + *pll1 =3D CRT_PLL1_HS_25MHZ; + *pll2 =3D CRT_PLL2_HS_25MHZ; + return; } =20 - /* if found none, we use default value */ - *pll1 =3D CRT_PLL1_HS_25MHZ; - *pll2 =3D CRT_PLL2_HS_25MHZ; + *pll1 =3D hibmc_pll_table[idx].pll1_config_value; + *pll2 =3D hibmc_pll_table[idx].pll2_config_value; } =20 /* @@ -319,7 +331,7 @@ static u32 display_ctrl_adjust(struct drm_device *dev, x =3D mode->hdisplay; y =3D mode->vdisplay; =20 - get_pll_config(x, y, &pll1, &pll2); + get_pll_config(mode, &pll1, &pll2); writel(pll2, priv->mmio + CRT_PLL2_HS); set_vclock_hisilicon(dev, pll1); =20 --=20 2.33.0