From nobody Tue Apr 7 18:33:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7182F390216; Thu, 12 Mar 2026 04:22:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773289322; cv=none; b=ACUKY7IwX6kahnOPgRsSfIDiwxHp4PR7XxTWq5DDzX4DokO89yPL9ZEe40gQzP3a2FHLGlSNC897LAKeCtfG++M0MhNZHOR0VnvIIeXNYs2shCGkl+D2gs2UdYcrBB5Qgt1wpx/eGL++slx3LAdFnRi4k1TVjJ/+O/qaao4OOXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773289322; c=relaxed/simple; bh=3wHXxRZW+3pyAHHF5bwYh0JQE5H6TZmyeNQhJB8UKIQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WEcU5IVe5nHrxgxixC90CMZvK7rjWLlhtxeqPwuhCmMGAObZ6HX17q3KN/vdteDh3rjOqI56Z7E6kNOZfRFV/90NGe++VKIJJs9tBDU97wAZI/c89goRK3+fNkfOI4xVPO6opzep0qYZZyst4zXmSbU1zcuSNY2hfv46DTFpiuY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hJpSuExt; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hJpSuExt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773289319; x=1804825319; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3wHXxRZW+3pyAHHF5bwYh0JQE5H6TZmyeNQhJB8UKIQ=; b=hJpSuExt6+83pL1ed52Ui3fqXkszKLDadM6A3FeJO2fxNFw6/LXSL+ex fl8yrMFyp3Bzo7qOk8hpxWDPBWYdv3vLCZd6S1emOyxJVN18plfNXvwe5 D8awTyFjOs8FbR57s+Xl3CHgBMfaWFjBfsn7TpfZkoavRros6GjyULqra fXLP8NvdYNZ4oxHVJvq6U+57RyBzwj1IbQo2D5CnXSpXmZOxC0PnGm0FA /h6siFZP2SfVZtMEpD3JRCduoKrfdW+ZTyiEbOzDGMbfD0RN+mGO749g6 InL0Fu0xTu+wEJORYFuNmFZ5v7Rz9bO+IQu5sBf1FF1FAJp1BEZ97LpC2 g==; X-CSE-ConnectionGUID: NZXECXbnSTC3akxw2a7kVQ== X-CSE-MsgGUID: n2UhO/M+TAONHhHV7VTwtw== X-IronPort-AV: E=Sophos;i="6.23,115,1770620400"; d="scan'208";a="62128084" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2026 21:21:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Wed, 11 Mar 2026 21:21:20 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 11 Mar 2026 21:21:11 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible Date: Thu, 12 Mar 2026 09:50:52 +0530 Message-ID: <20260312042056.309237-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260312042056.309237-1-manikandan.m@microchip.com> References: <20260312042056.309237-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Signed-off-by: Manikandan Muralidharan --- .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Docu= mentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..db659388a27d 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre =20 -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface =20 @@ -28,7 +25,9 @@ description: | =20 properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci reg: maxItems: 1 interrupts: @@ -39,6 +38,21 @@ required: - reg - interrupts =20 +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + required: + - clocks + unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Tue Apr 7 18:33:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFF8C394469; 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charset="utf-8" From: Durai Manickam KR Add peripheral clock description for I3C. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- changes in v3: - Fixed indentation issues --- drivers/clk/at91/sama7d65.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 7dee2b160ffb..ba8ff413fa2c 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -677,6 +677,7 @@ static struct { { .n =3D "uhphs_clk", .p =3D PCK_PARENT_HW_MCK5, .id =3D 101, }, { .n =3D "dsi_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 103, }, { .n =3D "lvdsc_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 104, }, + { .n =3D "i3cc_clk", .p =3D PCK_PARENT_HW_MCK8, .id =3D 105, }, }; =20 /* --=20 2.25.1 From nobody Tue Apr 7 18:33:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B08A396567; Thu, 12 Mar 2026 04:21:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773289309; cv=none; b=kxRelG1pukrtii2MUh4pc1EOHHNokTYs+PU7ZFNMfQyEP14UGkQ/JFsHWK/4EXEHQRtfP28rNx3byJ02JRSFQElPXSr0HlHSExSsdN8fWaUa+XnT74wgCT2nqUZ6zvSXQr/wk0Ry2dCoX7jpxHJz4u8UrQIEwJp63azHP6KFsm0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773289309; c=relaxed/simple; bh=Mfapho4KyK74MRDmiN5G9sod8x6U/8WWa0F9VXk3Lfo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UZ8Q/IHEW4rurMKmYQZlGgsRRWc0IlR2jySvLlYwuF7UmhLrkR1NSwMobinFtvxI9RiYlStbH+7DD34HyJPqy/+lj6G27v0ey/+nyR0jtiq+uVaAdry6XqYYvHwKQMd63Xxg5WKzYeWjIeJ+M+WzhLuxN33eYgjq4kX2DRA9Vp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Ib2/Tv7g; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ib2/Tv7g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773289306; x=1804825306; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mfapho4KyK74MRDmiN5G9sod8x6U/8WWa0F9VXk3Lfo=; b=Ib2/Tv7gJbgDLUS2eAk1qK8gtXxjvY8XbdmxbEyU45OakHoJtqwaZbNJ K7257E83N+RXus56QzAhmZOZGFpT9P5FJKrONn19033BatUyxojVv3+vB nGV6FtoryvJRkt70Cxqlra0NuWBTDsofmqwtVV8hOD552Lc4tzh+YV+rH EaApGR3acx7FFSXu+wKSltuJKzv7KUQIV5fbft5BqgDKTzC5yBB3msv3k ovWBWBTCwoeHSjLgzxqeajOUYw+OqF6x2wkLuxYi6DbZu7kumnGYliRvN gNt2WfuV2PVa2Zxu4qGgAWzaJWHB8C6VMXYmdWOgMH3NzbuVJL70IR7JN A==; X-CSE-ConnectionGUID: fvtvzCBGTY2f4cyuaBkSKA== X-CSE-MsgGUID: hKcz80kJRvGUhvYdZ4CKGQ== X-IronPort-AV: E=Sophos;i="6.23,115,1770620400"; d="scan'208";a="54551532" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 11 Mar 2026 21:21:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 11 Mar 2026 21:21:39 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 11 Mar 2026 21:21:30 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the appropriate quirk Date: Thu, 12 Mar 2026 09:50:54 +0530 Message-ID: <20260312042056.309237-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260312042056.309237-1-manikandan.m@microchip.com> References: <20260312042056.309237-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition for Microchip platforms using HCI_QUIRK_CLK_SUPPORT quirk. Introduce MCHP_I3C_CLK_IDX to define the maximum peripheral clock index Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files --- drivers/i3c/master/mipi-i3c-hci/core.c | 12 ++++++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 5879bba78164..6b7716bd517e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -918,6 +919,7 @@ static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata =3D pdev->dev.platform_dat= a; struct i3c_hci *hci; + struct clk_bulk_data *clks; int irq, ret; =20 hci =3D devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); @@ -946,6 +948,13 @@ static int i3c_hci_probe(struct platform_device *pdev) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks =3D platform_get_device_id(pdev)->driver_data; =20 + if (hci->quirks & HCI_QUIRK_CLK_SUPPORT) { + ret =3D devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < MCHP_I3C_CLK_IDX) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + } + ret =3D i3c_hci_init(hci); if (ret) return ret; @@ -971,6 +980,9 @@ static void i3c_hci_remove(struct platform_device *pdev) =20 static const __maybe_unused struct of_device_id i3c_hci_of_match[] =3D { { .compatible =3D "mipi-i3c-hci", }, + { .compatible =3D "microchip,sama7d65-i3c-hci", + .data =3D (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD | HCI_QUIRK_CLK_SUPPORT) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 337b7ab1cb06..2571ef6374ce 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -140,12 +140,16 @@ struct i3c_hci_dev_data { void *ibi_data; }; =20 +#define MCHP_I3C_CLK_IDX 2 /* Max peripheral clock index for Microchip pl= atforms */ + /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ +#define HCI_QUIRK_CLK_SUPPORT BIT(6) /* Enable Clocks for Microchip plat= forms*/ + =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); --=20 2.25.1 From nobody Tue Apr 7 18:33:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5962D4A23; Thu, 12 Mar 2026 04:22:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Durai Manickam KR Add I3C controller for sama7d65 SoC. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Remove clock-names property as driver enables the clk in bulk --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index e21556f46384..f358aae3ec59 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -1015,5 +1015,13 @@ gic: interrupt-controller@e8c11000 { #address-cells =3D <0>; interrupt-controller; }; + + i3c: i3c@e9000000 { + compatible =3D "microchip,sama7d65-i3c-hci"; + reg =3D <0xe9000000 0x300>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>; + status =3D "disabled"; + }; }; }; --=20 2.25.1 From nobody Tue Apr 7 18:33:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 717A235A3B9; Thu, 12 Mar 2026 04:22:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773289322; cv=none; b=U8b6APnEHXdXgJbV6IslQt3+hEJBtsq4+Zeq8AucIPfxQ+LZDNg6s4g8EYmdq9lw+EIWoa3JDgz9dAQVqO9veEf79h2Lou0ZZ6knM7QBcOCqyeRdT8MGCmPCuB98EYBWLxU6ylrNQfMl/9BJdTBgWtIlzKNXG5ZXCXLrArcs+80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773289322; c=relaxed/simple; bh=KhmIAgIkXR/FVGhINWVvBX+bl1GcxmHxs9BhpZObeTQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D/gs+HlHb113chR3zEfKlN40WTa6MAe1foCsRwLWQ9qbBBP8PiF/CiA/MPFiTWVcpI74L2PW6i5ict3h0VOg377qDktYRyhH+irhOLcc/mLjKSjKaeIzuMDVoyBg2oXcxZ+ufaILCbofTtd1UWcT1OjEFQmDlsM2COw3b4uiKQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PeVlUOU9; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PeVlUOU9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773289322; x=1804825322; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KhmIAgIkXR/FVGhINWVvBX+bl1GcxmHxs9BhpZObeTQ=; b=PeVlUOU9fYaqafbay8M2AxwNWo6O6tyrn5kyKC0jsXnRmwKVz2RMyOun Nm7Nyn84X/FmWw5+VJAc+NZID08DO/FtHSnf/uOp/FwOCE7o041GoNUAw c32iYm9ev+/fz1/u/6XtQBtTz7JCMp8wKyEAq9rDUBcwZ2p1L3MFFj+Dg LxMGX+ehaLTNXloWuwPAlUmkqopbAushPPABVcxmgnqaoQKG6lhjS8XX1 YoJCD1tUZ5af2jmtpC/D6w2yHhIzHn60+jcZa+d4tSY6OIgW3bnP946ft jUCBwYpvcxzLhScGQIqj2wBUeJ442xxSEiUpH3Nxd/xVCEhFn02e1J0Ju w==; X-CSE-ConnectionGUID: b4F98pPuQMeYoHXJAA3Q6w== X-CSE-MsgGUID: mp8RutGHQciMn0LqiiVDkQ== X-IronPort-AV: E=Sophos;i="6.23,115,1770620400"; d="scan'208";a="285933284" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2026 21:22:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Wed, 11 Mar 2026 21:21:58 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 11 Mar 2026 21:21:49 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: , Durai Manickam KR Subject: [PATCH v3 5/5] ARM: configs: at91: sama7: add sama7d65 i3c-hci Date: Thu, 12 Mar 2026 09:50:56 +0530 Message-ID: <20260312042056.309237-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260312042056.309237-1-manikandan.m@microchip.com> References: <20260312042056.309237-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Durai Manickam KR Enable the configs needed for I3C framework and microchip sama7d65 i3c-hci driver. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- arch/arm/configs/sama7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defc= onfig index e2ad9a05566f..a59b262e48e1 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -115,6 +115,8 @@ CONFIG_HW_RANDOM=3Dy CONFIG_I2C=3Dy CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_AT91=3Dy +CONFIG_I3C=3Dy +CONFIG_MIPI_I3C_HCI=3Dy CONFIG_SPI=3Dy CONFIG_SPI_ATMEL=3Dy CONFIG_SPI_ATMEL_QUADSPI=3Dy --=20 2.25.1