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(unknown [210.73.43.101]) by APP-05 (Coremail) with SMTP id zQCowAAntwqkFLJpB6U4Cg--.65391S4; Thu, 12 Mar 2026 09:19:34 +0800 (CST) From: Jiakai Xu To: kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Jiakai Xu , Jiakai Xu , Andrew Jones Subject: [PATCH v4 2/2] RISC-V: KVM: selftests: Fix firmware counter read in sbi_pmu_test Date: Thu, 12 Mar 2026 01:19:31 +0000 Message-Id: <20260312011931.1352239-3-xujiakai2025@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260312011931.1352239-1-xujiakai2025@iscas.ac.cn> References: <20260312011931.1352239-1-xujiakai2025@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAAntwqkFLJpB6U4Cg--.65391S4 X-Coremail-Antispam: 1UD129KBjvJXoWxGw4ftFW7ZFWkXFWDZF1DWrg_yoWrArWkpF W8JFWYkrWrtFnFyFy3A3ZFgr1UXan3Za47KrW7Wry2yr4UZryfXwsIgF9Fyan8CFZYg343 Aw1Iga1rCF47JaUanT9S1TB71UUUUjDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUlY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0 owAaw2AFwI0_JF0_Jw1lnxkEFVAIw20F6cxK64vIFxWle2I262IYc4CY6c8Ij28IcVAaY2 xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2 jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5V A0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_ Wrylc2xSY4AK67AK6w4l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4I xYO2xFxVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWU GVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI 0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xva j40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JV W8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRixpnPUUUUU== X-CM-SenderInfo: 50xmxthndljiysv6x2xfdvhtffof0/1tbiDAYECWmx5uuPyQAAsU Content-Type: text/plain; charset="utf-8" The current sbi_pmu_test attempts to read firmware counters without configuring them first with SBI_EXT_PMU_COUNTER_CFG_MATCH. Previously this did not fail because KVM incorrectly allowed the read and accessed fw_event[] with an out-of-bounds index when the counter was unconfigured. After fixing that bug, the read now correctly returns SBI_ERR_INVALID_PARAM, causing the selftest to fail. Update the test to configure a firmware event before reading the counter. Also add a negative test to ensure that attempting to read an unconfigured firmware counter fails gracefully. Signed-off-by: Jiakai Xu Signed-off-by: Jiakai Xu Reviewed-by: Andrew Jones --- V2 -> V3: - Removed unnecessary BIT(ret.value) & counter_mask_available check. - Asserted ret.value =3D=3D i after successful CFG_MATCH. - Fixed eidx construction in SBI_EXT_PMU_COUNTER_CFG_MATCH. --- .../testing/selftests/kvm/include/riscv/sbi.h | 37 +++++++++++++++++++ .../selftests/kvm/riscv/sbi_pmu_test.c | 20 +++++++++- 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testin= g/selftests/kvm/include/riscv/sbi.h index 046b432ae896..16f1815ac48f 100644 --- a/tools/testing/selftests/kvm/include/riscv/sbi.h +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -97,6 +97,43 @@ enum sbi_pmu_hw_generic_events_t { SBI_PMU_HW_GENERAL_MAX, }; =20 +enum sbi_pmu_fw_generic_events_t { + SBI_PMU_FW_MISALIGNED_LOAD =3D 0, + SBI_PMU_FW_MISALIGNED_STORE =3D 1, + SBI_PMU_FW_ACCESS_LOAD =3D 2, + SBI_PMU_FW_ACCESS_STORE =3D 3, + SBI_PMU_FW_ILLEGAL_INSN =3D 4, + SBI_PMU_FW_SET_TIMER =3D 5, + SBI_PMU_FW_IPI_SENT =3D 6, + SBI_PMU_FW_IPI_RCVD =3D 7, + SBI_PMU_FW_FENCE_I_SENT =3D 8, + SBI_PMU_FW_FENCE_I_RCVD =3D 9, + SBI_PMU_FW_SFENCE_VMA_SENT =3D 10, + SBI_PMU_FW_SFENCE_VMA_RCVD =3D 11, + SBI_PMU_FW_SFENCE_VMA_ASID_SENT =3D 12, + SBI_PMU_FW_SFENCE_VMA_ASID_RCVD =3D 13, + + SBI_PMU_FW_HFENCE_GVMA_SENT =3D 14, + SBI_PMU_FW_HFENCE_GVMA_RCVD =3D 15, + SBI_PMU_FW_HFENCE_GVMA_VMID_SENT =3D 16, + SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD =3D 17, + + SBI_PMU_FW_HFENCE_VVMA_SENT =3D 18, + SBI_PMU_FW_HFENCE_VVMA_RCVD =3D 19, + SBI_PMU_FW_HFENCE_VVMA_ASID_SENT =3D 20, + SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD =3D 21, + SBI_PMU_FW_MAX, +}; + +/* SBI PMU event types */ +enum sbi_pmu_event_type { + SBI_PMU_EVENT_TYPE_HW =3D 0x0, + SBI_PMU_EVENT_TYPE_CACHE =3D 0x1, + SBI_PMU_EVENT_TYPE_RAW =3D 0x2, + SBI_PMU_EVENT_TYPE_RAW_V2 =3D 0x3, + SBI_PMU_EVENT_TYPE_FW =3D 0xf, +}; + /* SBI PMU counter types */ enum sbi_pmu_ctr_type { SBI_PMU_CTR_TYPE_HW =3D 0x0, diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 924a335d2262..9404577e4ad5 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -436,6 +436,7 @@ static void test_pmu_basic_sanity(void) struct sbiret ret; int num_counters =3D 0, i; union sbi_pmu_ctr_info ctrinfo; + unsigned long fw_eidx; =20 probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); GUEST_ASSERT(probe && out_val =3D=3D 1); @@ -461,7 +462,24 @@ static void test_pmu_basic_sanity(void) pmu_csr_read_num(ctrinfo.csr); GUEST_ASSERT(illegal_handler_invoked); } else if (ctrinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { - read_fw_counter(i, ctrinfo); + /* Read without configure should fail */ + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, + i, 0, 0, 0, 0, 0); + GUEST_ASSERT(ret.error =3D=3D SBI_ERR_INVALID_PARAM); + + /* + * Try to configure with a common firmware event. + * If configuration succeeds, verify we can read it. + */ + fw_eidx =3D ((unsigned long)SBI_PMU_EVENT_TYPE_FW << 16) | + SBI_PMU_FW_ACCESS_LOAD; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, + i, 1, 0, fw_eidx, 0, 0); + if (ret.error =3D=3D 0) { + GUEST_ASSERT(ret.value =3D=3D i); + read_fw_counter(i, ctrinfo); + } } } =20 --=20 2.34.1