From nobody Tue Apr 7 18:03:29 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 581603CF02A for ; Thu, 12 Mar 2026 13:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773322217; cv=none; b=ni5+frYoFncyYkGNJffzH2KBmnKtUdEG+06DVCtP3/X4C4L46iIJrk5WAbvPwRB39ws9hMEjzzOvOnldBNB+oIYS2rjDJvpKRhO2C6EVD39fnHeGjW5mI7/LxybmWbm751BfUD/+B2Tr+wT1JbNTabZ/Bp3slndpql+OJiBr4WQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773322217; c=relaxed/simple; bh=Qu7SCbd08U0FxPNSARkgsOS6vFM+FAyy6vsMyoASvXA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HSy7BYKPlnj6wsPx70pLg214CKEQS9HU7Nre+IA9vq10TjgcnXGnyDMuxZbyEvMODA2a0hzXvCMQbETo3qhc1q0QWFIv8xqJNGw0PkXCddkRsLpBqqfn8MOCtbRi+jJ5bEtSJdwRHpZauvb1RbMxFkI/42futeCh0EPDuecWuqw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Vgzz65OX; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=D1+qtYYz; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Vgzz65OX"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="D1+qtYYz" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62C9kgWp4132843 for ; Thu, 12 Mar 2026 13:30:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4kJnWK+0X3yWbB1kK40cUekEe/em44tg5c3VSKIz4Wo=; b=Vgzz65OX9KYFnj8M SWl4zaP6YGD4JgHFyi+ToE2EFY0Y4WCF2ZdlYH26WhN0hBb05ZIvWlIO7QzykSO5 I8gqaPb9MaPl2lwezKjVwd6C/83TsViCQX+vF9EcVAKiW4RnmWkBxsd16A4fbMyP MjTWh8/nRXDBAQccdrUltzsaug3XLomq/hStoaW5ejQ40Q7lGNNmNcZwFBaQn29D BwiBjk34oALQQAItvThGe3/Mnbny+oz4KwX+TLyEPpjSPluuD/HFTTyJzlndttia RxFH2hYmCbIuK8xZvWaaqqO1HVZ5X22MHuzkmsUzjeWZiIRXAI7Nq4RR1LmkJPw4 7/5Y3w== Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cuh4w26kn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 12 Mar 2026 13:30:15 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-8cd77bc8186so994227585a.0 for ; Thu, 12 Mar 2026 06:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773322214; x=1773927014; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4kJnWK+0X3yWbB1kK40cUekEe/em44tg5c3VSKIz4Wo=; b=D1+qtYYz5/VSw/vGBXLo2GjjNxKbjFQNi1G7MpbBvTOBSYdHUag0loxFjv+coUBQhT uf0eMSalNxHNoGqPa0fL+VCLsKo3MjfeuOEPNn5RcEHsoXK4Gw0VQlvER5n7TJ1wVY6o askmROd8Q6k3uNIlksbiH2QFLMSunSIHrhpue2Bkx5ZqvVL54hxfLUgPiJR7hYaF0YJV 9lOTRsBkGMyHu/UIf6+sfM0rAt+kfPKnfuRn8Cj1/njVfOKrTVn4nx6OrhQIZb9w2UKN 3Xh/FEyKLObiIyO+EIN9ILFyDXFnyPCQWrGz+p6odg/IKi3KSDW1aN32efTyuKvvVe1I ONKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773322214; x=1773927014; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4kJnWK+0X3yWbB1kK40cUekEe/em44tg5c3VSKIz4Wo=; b=iECTD6uP46kwgQHn/4xZ7UNchbrDJkVIRAZ52L89A6M+A/s97UYNqLuDvLOFvd4obr Uqt04ptk4wvR1A2DjNgvqyqrGelRiBG9pqe0rtBgM34foBFKKAcUP3oPYPxGZAtOuKOd wPWWwo44GyFtBDy3nA9Hi9hVQnt1YK/ugl0T5q4yX889aA9OZDNJ2xkvzfmyEdbWC72x 7h3GYVFsrGMHgoxL41ojTWX6ODMkbbM+hHkcNFZg+oRrpHB1e4NJ3N9HBiCM1M67E1FF QadtYN1kngvYe7271A+c37bbaXwgljagb6erbK428pEySjT7sckll6r1whstA9eVWGAs icJw== X-Forwarded-Encrypted: i=1; AJvYcCWgjUuvLpfSyoouD1LJIA62W5j2E0spo5Jlbdhl/3O0YS/MQS9fv/+BJAq/nKmUZyZl4CIBrQv/m9aTk3s=@vger.kernel.org X-Gm-Message-State: AOJu0YypJVyfxq5olXREj73J0tfbkncDof0XKPZajBBH9KSkX6IuluCV M4zG2IdBnu5cUm+rv9rEhrCsKKUyoEccEAQ/w+fdS07FvQpU0pwANLMyl/bau+AL6Et/SBd/IYN wk4Vl4ImCAf2WgR+VuRcfxNaDYS6C4tKoFD8jT4+00Y5drTnitmJbk/2fjBT2QDWgZZs= X-Gm-Gg: ATEYQzwdR88RpkmricGnXTKO2/Kh5Sl6WM/ZLDClQRal55taVWaznyS+Dj4RNtc5+gL eWIur5wywp8K+b7HIyH80TLymuSvrGJpaXuQ7FpFweMmDZHWw3ojWRi2mxi9miqf3QCq1tCzERH 9lkxwkbTFuTaQllmduXnRCWbyApS56CEAJ7gUyuEy2bFLIyma5uoJHJxO67Rfl2TYFBpWfaTovr DSb76NSyknxpZh8oaoFT5dmAD3Drcy1BAYRlT/G+3r6sT+g4+0DRnokawnoB2+tNIiYnFVKkcOn R1rifXJo/09uGc2Go5ALf81gPos46f5MAct/BN3MXIYAiwKfpSZKK49oKpEX5nKCs1ubFoH1IhH PSEfCziLbOnSy2EM2mhEjda00Tt6VxC5aHvhndrdXYudwqCzrqjaCFA0GQLD9g5rcZH5xrz4fCH 6cT6fp8FBR5GJrXc1SiO9EoKkqe6QddEWMxNY= X-Received: by 2002:a05:620a:7112:b0:8cd:96e5:f7c8 with SMTP id af79cd13be357-8cda1a559cdmr766513185a.57.1773322214059; Thu, 12 Mar 2026 06:30:14 -0700 (PDT) X-Received: by 2002:a05:620a:7112:b0:8cd:96e5:f7c8 with SMTP id af79cd13be357-8cda1a559cdmr766502585a.57.1773322213412; Thu, 12 Mar 2026 06:30:13 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67d617e1sm8646671fa.9.2026.03.12.06.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 06:30:12 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 12 Mar 2026 15:29:46 +0200 Subject: [PATCH v3 25/27] soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260312-ubwc-rework-v3-25-b7e8f800176a@oss.qualcomm.com> References: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> In-Reply-To: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6082; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Qu7SCbd08U0FxPNSARkgsOS6vFM+FAyy6vsMyoASvXA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsr+4mKKhz4P253cyaZOGYWl46uL+Qn4OOtS8h lh2uw5D9NeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabK/uAAKCRCLPIo+Aiko 1RWRCACJ7gDjMdRfrJBykdoGT9vzRU982M9SLzPBR1PaPDZ0Jnn7Aoriafu7jdgUdgUPCD+XK3n XO5EdIDxSWiSGKwhTa/AawvYsjEAmAI/9ec7TOlTxOw4ODf/i/Ooh45lRmhGvCbQFJAbVb0XfLs 2mY2+s1c0N2SdFzQ5CzpsvjpnZu4EM/sMjKFtBoyzm7rcmffl2pceUMts4eDJyc/ab9ajJxO0Vq IgSsYPspLbX8RETu2YtsvzPJAm3OT2SwKvEtTxiovg6xi5CsB+2QdZyi9ijTGH6LNW96Bas3KQi 4BSkPXWJT31aI4PkObeGcM0q+3QEQQLbUQju9fzJAwCEik7Q X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: S4PzvpVu3roPoklFju0uQK3leIoK8TIh X-Authority-Analysis: v=2.4 cv=Cpays34D c=1 sm=1 tr=0 ts=69b2bfe7 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=8a_ODPMxA7UucN5sxwIA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: S4PzvpVu3roPoklFju0uQK3leIoK8TIh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEyMDEwNyBTYWx0ZWRfX0wFVdufpUCvu +eMYvnOe8QG6tnaUs8HKtpq1nSMW6UjS4O64XL3GzYe7WhPoCLwymKtw1I1dHUeEicbHHzYURWI cBwQjwB1dHEVgChT6GjmlsCjN3ruQTBx3djiCFN74Hkg1Ozru6ryoDHsr0U1n7KfqGKMb0n5gn0 mlpuZ3GBh9sviRCoOIjvw+mwqcnYjU8HEjNhNNzpiGJFzyT+sphU0fuc7B7SFKcDw1Sr11k2gk5 zaH9OdU4KWzQe0wlKEyhRI0BRhdcW4BSdLSrVUEX8Xy0+Hwxc9Q5Gt3GcNYjHP1wWwPKuMEn+NJ hPR9FY6vvNSDpp8Ocwz/cBuTC3aDBYWpgSiclRL1Wl6lrKunq/0eQIl63KsjBZLl3lZRfUGSN4a ktWu318gj0Bpw32MEV0T13NO3mW8B8wr8DQvY9h7bFBVbJ0l7raH6gHJvnAopOLcA9MFRyV7+31 T0nJ4EidqMV1bEgXJLA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603120107 UBWC devices before 4.0 use standard UBWC swizzle levels. As all the drivers now use the qcom_ubwc_swizzle() helper, move those values to the helper, leaving UBWC 4.0+ intact for now. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 34 ---------------------------------- include/linux/soc/qcom/ubwc.h | 33 ++++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 43 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 51de36f5f40b..49edfabb5e18 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -25,17 +25,11 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = =3D { =20 static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 @@ -52,94 +46,66 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D= { =20 static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_1, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 13, }; =20 static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_1, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, }; =20 static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, }; =20 static const struct qcom_ubwc_cfg_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index fee778360ac2..7c9506741001 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -22,9 +22,6 @@ struct qcom_ubwc_cfg_data { * UBWC 4.0 adds the optional ability to disable levels 2 & 3. */ u32 ubwc_swizzle; -#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) -#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) -#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) =20 /** * @highest_bank_bit: Highest Bank Bit @@ -55,12 +52,7 @@ static inline const struct qcom_ubwc_cfg_data *qcom_ubwc= _config_get_data(void) =20 static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data= *cfg) { - bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; - - if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) - pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); - - return ret; + return cfg->ubwc_enc_version =3D=3D UBWC_1_0; } =20 static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg= _data *cfg) @@ -85,8 +77,31 @@ static inline bool qcom_ubwc_bank_spread(const struct qc= om_ubwc_cfg_data *cfg) return true; } =20 +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) + +/** + * @qcom_ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. + * + * UBWC 1.0 always enables all three levels. + * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. + * UBWC 4.0 adds the optional ability to disable levels 2 & 3. + */ static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) { + if (cfg->ubwc_enc_version =3D=3D 0) + return 0; + + if (cfg->ubwc_enc_version =3D=3D UBWC_1_0) + return UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3; + + if (cfg->ubwc_enc_version < UBWC_4_0) + return UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3; + return cfg->ubwc_swizzle; } =20 --=20 2.47.3