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Wed, 11 Mar 2026 23:49:16 +0000 X-MS-Exchange-Authentication-Results: spf=softfail (sender IP is 91.26.50.189) smtp.mailfrom=phytec.de; dkim=none (message not signed) header.d=none;dmarc=fail action=quarantine header.from=phytec.de; Received-SPF: SoftFail (protection.outlook.com: domain of transitioning phytec.de discourages use of 91.26.50.189 as permitted sender) Received: from Postix.phytec.de (91.26.50.189) by AM4PEPF00025F9A.mail.protection.outlook.com (10.167.16.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.1 via Frontend Transport; Wed, 11 Mar 2026 23:49:12 +0000 Received: from lws-haller-privat.phytec.de (172.25.39.212) by Postix.phytec.de (172.25.0.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.35; Thu, 12 Mar 2026 00:49:09 +0100 From: Dominik Haller To: Nishanth Menon , Vignesh Raghavendra , "Tero Kristo" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , , "Dominik Haller" Subject: [PATCH v3 3/5] arm64: dts: ti: k3-am68-phyboard-izar: Add LVDS-Display Date: Wed, 11 Mar 2026 16:48:39 -0700 Message-ID: <20260311234844.56443-4-d.haller@phytec.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311234844.56443-1-d.haller@phytec.de> References: <20260311234844.56443-1-d.haller@phytec.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: Postix.phytec.de (172.25.0.11) To Postix.phytec.de (172.25.0.11) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00025F9A:EE_|GVXP195MB2481:EE_ X-MS-Office365-Filtering-Correlation-Id: a8037f72-bd60-4c2b-d751-08de7fc8cc1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|56012099003|22082099003|18002099003; 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charset="utf-8" Add an overlay to use a powertip,ph128800t006-zhc01 10.1" LVDS display. Signed-off-by: Dominik Haller --- arch/arm64/boot/dts/ti/Makefile | 4 + ...-am68-phyboard-izar-lvds-ph128800t006.dtso | 125 ++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128= 800t006.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index ba01a929e06f..a188e62e32b4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -132,6 +132,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk-csi2-dual-imx219= .dtbo =20 # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar-lvds-ph128800t006.dtb +k3-am68-phyboard-izar-lvds-ph128800t006-dtbs :=3D k3-am68-phyboard-izar.dt= b \ + k3-am68-phyboard-izar-lvds-ph128800t006.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb @@ -319,6 +322,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am67a-kontron-sa67-base-gpios.dtb \ + k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006= .dtso b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso new file mode 100644 index 000000000000..f167d6cc43e7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + backlight_lvds: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 32 64 96 128 160 192 224 255>; + default-brightness-level =3D <6>; + enable-gpios =3D <&exp2 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&backlight_pins_default>; + power-supply =3D <&bl_12v>; + pwms =3D <&main_ehrpwm0 1 44000 0>; + }; + + bl_12v: regulator-backlight { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&exp2 13 GPIO_ACTIVE_HIGH>; + regulator-name =3D "BL_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + panel-lvds { + compatible =3D "powertip,ph128800t006-zhc01"; + backlight =3D <&backlight_lvds>; + power-supply =3D <&vcc_5v0>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&panel_bridge_out>; + }; + }; + }; +}; + +&main_pmx0 { + backlight_pins_default: backlight-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x064, PIN_OUTPUT, 9) /* (W28) MCAN0_TX.EHRPWM0_B */ + >; + }; +}; + +&dphy_tx0 { + status =3D "okay"; +}; + +&dss { + status =3D "okay"; +}; + +&dss_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + dpi2_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; +}; + +&dsi0 { + status =3D "okay"; +}; + +&dsi0_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_out: endpoint { + remote-endpoint =3D <&panel_bridge_in>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpi2_out>; + }; + }; +}; + +&main_ehrpwm0 { + status =3D "okay"; +}; + +&sn65dsi83 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + panel_bridge_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + data-lanes =3D <1 2 3 4>; + }; + }; + + port@2 { + reg =3D <2>; + panel_bridge_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; --=20 2.43.0