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charset="utf-8" Assign the dss clocks in the base dts so that display overlays can be used in any combination. Signed-off-by: Dominik Haller --- .../boot/dts/ti/k3-am68-phyboard-izar.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/= boot/dts/ti/k3-am68-phyboard-izar.dts index e221ccb30e95..b8d17bdb7685 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts @@ -298,6 +298,24 @@ phy0: ethernet-phy@0 { }; }; =20 +&dss { + /* + * VP0 - Displayport + * VP1 - DPI0 + * VP2 - DSI0 + * VP3 - DPI1/DSI1 + */ + + assigned-clocks =3D <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + assigned-clock-parents =3D <&k3_clks 158 3>, + <&k3_clks 158 7>, + <&k3_clks 158 16>, + <&k3_clks 158 22>; +}; + &i2c_som_rtc { trickle-resistor-ohms =3D <3000>; }; --=20 2.43.0 From nobody Tue Apr 7 18:33:28 2026 Received: from AM0PR02CU008.outbound.protection.outlook.com (mail-westeuropeazon11023098.outbound.protection.outlook.com [52.101.72.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3B5837703C; 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charset="utf-8" Add the TI SN65DSI83 MIPI-DSI->LVDS bridge that can be populated on the phyCORE-AM68x/TDA4x. Signed-off-by: Dominik Haller --- arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am68-phycore-som.dtsi index 0ff511028f81..ab87767419fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -151,6 +151,12 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27)= WKUP_I2C0_SDA */ >; bootph-all; }; + + wkup_sn65dsi83_pins_default: wkup-sn65dsi83-default-pins { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x084, PIN_OUTPUT, 7) /* (F25) WKUP_GPIO0_11 */ + >; + }; }; =20 &main_cpsw { @@ -183,6 +189,17 @@ &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; =20 + sn65dsi83: bridge@2d { + compatible =3D "ti,sn65dsi83"; + reg =3D <0x2d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_sn65dsi83_pins_default>; + enable-gpios =3D <&wkup_gpio0 11 GPIO_ACTIVE_LOW>; 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charset="utf-8" Add an overlay to use a powertip,ph128800t006-zhc01 10.1" LVDS display. Signed-off-by: Dominik Haller --- arch/arm64/boot/dts/ti/Makefile | 4 + ...-am68-phyboard-izar-lvds-ph128800t006.dtso | 125 ++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128= 800t006.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index ba01a929e06f..a188e62e32b4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -132,6 +132,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk-csi2-dual-imx219= .dtbo =20 # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar-lvds-ph128800t006.dtb +k3-am68-phyboard-izar-lvds-ph128800t006-dtbs :=3D k3-am68-phyboard-izar.dt= b \ + k3-am68-phyboard-izar-lvds-ph128800t006.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb @@ -319,6 +322,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am67a-kontron-sa67-base-gpios.dtb \ + k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006= .dtso b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso new file mode 100644 index 000000000000..f167d6cc43e7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + backlight_lvds: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 32 64 96 128 160 192 224 255>; + default-brightness-level =3D <6>; + enable-gpios =3D <&exp2 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&backlight_pins_default>; + power-supply =3D <&bl_12v>; + pwms =3D <&main_ehrpwm0 1 44000 0>; + }; + + bl_12v: regulator-backlight { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&exp2 13 GPIO_ACTIVE_HIGH>; + regulator-name =3D "BL_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + panel-lvds { + compatible =3D "powertip,ph128800t006-zhc01"; + backlight =3D <&backlight_lvds>; + power-supply =3D <&vcc_5v0>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&panel_bridge_out>; + }; + }; + }; +}; + +&main_pmx0 { + backlight_pins_default: backlight-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x064, PIN_OUTPUT, 9) /* (W28) MCAN0_TX.EHRPWM0_B */ + >; + }; +}; + +&dphy_tx0 { + status =3D "okay"; +}; + +&dss { + status =3D "okay"; +}; + +&dss_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + dpi2_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; +}; + +&dsi0 { + status =3D "okay"; +}; + +&dsi0_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_out: endpoint { + remote-endpoint =3D <&panel_bridge_in>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpi2_out>; + }; + }; +}; + +&main_ehrpwm0 { + status =3D "okay"; +}; + +&sn65dsi83 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + panel_bridge_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + data-lanes =3D <1 2 3 4>; + }; + }; + + port@2 { + reg =3D <2>; + panel_bridge_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; --=20 2.43.0 From nobody Tue Apr 7 18:33:28 2026 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11023130.outbound.protection.outlook.com [40.107.159.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF16237A489; 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charset="utf-8" Add the second DSI instance and its corresponding phy to the main domain include file. Signed-off-by: Dominik Haller Reviewed-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 80c51b11ac9f..80a32c451d1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1815,6 +1815,19 @@ dphy_tx0: phy@4480000 { status =3D "disabled"; }; =20 + dphy_tx1: phy@4481000 { + compatible =3D "ti,j721e-dphy"; + reg =3D <0x00 0x04481000 0x00 0x00001000>; + clocks =3D <&k3_clks 364 8>, <&k3_clks 364 14>; + clock-names =3D "psm", "pll_ref"; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 364 14>; + assigned-clock-parents =3D <&k3_clks 364 15>; + assigned-clock-rates =3D <19200000>; + status =3D "disabled"; + }; + dsi0: dsi@4800000 { compatible =3D "ti,j721e-dsi"; reg =3D <0x00 0x04800000 0x00 0x00100000>, @@ -1841,6 +1854,32 @@ port@1 { }; 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charset="utf-8" Add an overlay to use the PEB-AV-15 AV-Adapter. It's a small expansion board using a Lontium LT8912B DSI->HDMI bridge and a TLV320AIC3007 audio codec. Signed-off-by: Dominik Haller --- arch/arm64/boot/dts/ti/Makefile | 4 + .../ti/k3-am68-phyboard-izar-peb-av-15.dtso | 192 ++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.= dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index a188e62e32b4..ae5994818ad2 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -135,6 +135,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar-lvds-ph128800t006.dtb k3-am68-phyboard-izar-lvds-ph128800t006-dtbs :=3D k3-am68-phyboard-izar.dt= b \ k3-am68-phyboard-izar-lvds-ph128800t006.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-phyboard-izar-peb-av-15.dtb +k3-am68-phyboard-izar-peb-av-15-dtbs :=3D k3-am68-phyboard-izar.dtb \ + k3-am68-phyboard-izar-peb-av-15.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb @@ -323,6 +326,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am67a-kontron-sa67-base-gpios.dtb \ k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ + k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.dtso b/= arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.dtso new file mode 100644 index 000000000000..a86971fcdee1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.dtso @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + audio_refclk1: audio-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + }; + + hdmi: hdmi-connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "a"; + ddc-i2c-bus =3D <&main_i2c2>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <<8912b_out>; + }; + }; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCC3V3_AUDIO"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCC1V8_AUDIO"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "PEB-AV-15"; + simple-audio-card,widgets =3D + "Headphone", "Headphone Jack", + "Microphone", "Mic Jack"; + simple-audio-card,routing =3D + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias"; + simple-audio-card,format =3D "dsp_b"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master =3D <&link0_codec>; + simple-audio-card,frame-master =3D <&link0_codec>; + + link0_cpu: simple-audio-card,cpu { + sound-dai =3D <&mcasp0>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai =3D <&audio_codec>; + clocks =3D <&audio_refclk1>; + }; + }; + +}; + +&dphy_tx1 { + status =3D "okay"; +}; + +&dsi1 { + status =3D "okay"; +}; + +&dsi1_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + dsi1_out: endpoint { + remote-endpoint =3D <<8912b_in>; + }; + }; + + port@1 { + reg =3D <1>; + dsi1_in: endpoint { + remote-endpoint =3D <&dpi3_out>; + }; + }; +}; + +&dss { + status =3D "okay"; +}; + +&dss_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@3 { + reg =3D <3>; + dpi3_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; +}; + +&mcasp0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcasp0_pins>; + + #sound-dai-cells =3D <0>; + + op-mode =3D <0>; /* MCASP_IIS_MODE */ + tdm-slots =3D <2>; + + /* 4 serializers */ + serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ + 2 0 0 1 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + + tx-num-evt =3D <32>; + rx-num-evt =3D <32>; + status =3D "okay"; +}; + +&main_i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + audio_codec: audio-codec@18 { + compatible =3D "ti,tlv320aic3007"; + reg =3D <0x18>; + #sound-dai-cells=3D <0>; + ai3x-micbias-vg =3D <2>; + AVDD-supply =3D <®_audio_3v3>; + IOVDD-supply =3D <®_audio_3v3>; + DRVDD-supply =3D <®_audio_3v3>; + DVDD-supply =3D <®_audio_1v8>; + + }; + + bridge@48 { + compatible =3D "lontium,lt8912b"; + reg =3D <0x48>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + lt8912b_in: endpoint { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&dsi1_out>; + }; + }; + + port@1 { + reg =3D <1>; + lt8912b_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_pmx0 { + mcasp0_pins: mcasp0-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x03c, PIN_INPUT, 1) /* (U27) WCLK, MCASP0_AFSX.MCASP0_AFS= X */ + J721S2_IOPAD(0x038, PIN_INPUT, 1) /* (AB28) BCLK, MCASP0_ACLKX.MCASP0_A= CLKX */ + J721S2_IOPAD(0x040, PIN_OUTPUT, 1) /* (AC28) DOUT, MCASP0_AXR0.MCASP0_A= XR0 */ + J721S2_IOPAD(0x07c, PIN_INPUT, 1) /* (T27) DIN, MCASP0_AXR3.MCASP0_AXR3= */ + >; + }; +}; --=20 2.43.0