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Wed, 11 Mar 2026 13:35:20 -0700 From: To: , , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 04/20] cxl: Media ready check refactoring Date: Thu, 12 Mar 2026 02:04:24 +0530 Message-ID: <20260311203440.752648-5-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260311203440.752648-1-mhonap@nvidia.com> References: <20260311203440.752648-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636A:EE_|PH7PR12MB6833:EE_ X-MS-Office365-Filtering-Correlation-Id: c9355dd6-e280-42fd-6a0a-08de7fadca3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|1800799024|376014|36860700016|56012099003|22082099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: of2LLsAGqtUtV455hk31HJSxc6GR3j8DPwHHpciuPbDGtD5qIbPJ6f+IDQ4QTRRqnXStJBFhOat5ZNHR44Vkd5ZSzH8DA/+RfZQ1P4fzCFwjobHiDu6+HYatrGIjIRvmxsj9XE9o8Zfn47BHFs6pN42UbP6upO+N2Ii4vFI0AlR+ngK516igJiHzYK2wu9B7A+Fo/VkEvGjIdCGnlQc67YJTSi2/mbSIs4KDfRIgXJBIk3Jzvdd6debBNHy/CrisSNEhezZdRF3MLGiMF50mJ2D11bxtR+g3E+QHRyQlMFHDA4/3ED4d+vV6KGoB7AlYKrtKYIAGXCW4X6edvoLwEfDl4ZK/vwC/6n7r5ymAJz7PJD/wPEESrdRxPNLDMDqZIq2ModkZZULau8Ajp/QUR8P9WUiXL9CxVhyTSAC99r3eK3Hgwq7le4sm2rmvwJGV9Z0cYBX+Mz0yNPPQe06c9xq+WWcEvCppnG3zhluGZAwHarYupBKL8KMViK7FrzqcyBwkb0FKMn4pLdRcrO1gQWRDdlL8gLnubUkEcGXoDM8fRXgZ2t0y9Qeb1cP7CvIgLqEjz7P1WhKgHe8ZUrEaDWJKC9aTWdNYnqc55GOzmRolqVEXrajimxY/ZvBPStv296SURK2bMRCd/xdnXpKswPJ7RPzyqUGbTFRNdhtGYMDjNN6i99cD4iXp96GRWfoAIUFds3tYGzAuiarFvycOZorKOVlwAY+oZwSnQGQABxWsHqFq+LIDVQBrOlRplyZbaNC/g7KM4/S011AwFuG+XA6wxHCF+kpW1DhMyO/MvRrcZ3PFqWN2pTKgFcGZ9YlK X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(1800799024)(376014)(36860700016)(56012099003)(22082099003)(18002099003)(921020);DIR:OUT;SFP:1101; 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charset="utf-8" From: Manish Honap Before accessing CXL device memory after reset/power-on, the driver must ensure media is ready. Not every CXL device implements the CXL Memory Device register group (many Type-2 devices do not). cxl_await_media_ready() reads cxlds->regs.memdev; calling it on a Type-2 without that block can result in kernel panic. This commit refactors the HDM range based check in a new function which can be safely used for type-2 and type-3 devices. cxl_await_media_ready still uses the same format of checking the HDM range and memory device register status. Co-developed-by: Zhi Wang Signed-off-by: Zhi Wang Signed-off-by: Manish Honap Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 35 ++++++++++++++++++++++++++++++----- include/cxl/cxl.h | 1 + 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 52ed0b4f5e78..2b7e4d73a6dd 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -142,16 +142,24 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_= state *cxlds, int id) return 0; } =20 -/* - * Wait up to @media_ready_timeout for the device to report memory - * active. +/** + * cxl_await_range_active - Wait for all HDM DVSEC memory ranges to be act= ive + * @cxlds: CXL device state (DVSEC and HDM count must be valid) + * + * For each HDM decoder range reported in the CXL DVSEC capability, waits = for + * the range to report MEM INFO VALID (up to 1s per range), then MEM ACTIVE + * (up to media_ready_timeout seconds per range, default 60s). Used by + * cxl_await_media_ready() and by callers that only need range readiness + * without checking the memory device status register. + * + * Return: 0 if all ranges become valid and active, -ETIMEDOUT if a timeout + * occurs, or a negative errno from config read on failure. */ -int cxl_await_media_ready(struct cxl_dev_state *cxlds) +int cxl_await_range_active(struct cxl_dev_state *cxlds) { struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); int d =3D cxlds->cxl_dvsec; int rc, i, hdm_count; - u64 md_status; u16 cap; =20 rc =3D pci_read_config_word(pdev, @@ -172,6 +180,23 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) return rc; } =20 + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_await_range_active, "CXL"); + +/* + * Wait up to @media_ready_timeout for the device to report memory + * active. + */ +int cxl_await_media_ready(struct cxl_dev_state *cxlds) +{ + u64 md_status; + int rc; + + rc =3D cxl_await_range_active(cxlds); + if (rc) + return rc; + md_status =3D readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); if (!CXLMDEV_READY(md_status)) return -EIO; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 27c006fa53c3..684603799fb1 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -323,5 +323,6 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_re= gloc_type type, struct cxl_register_map *map); void cxl_probe_component_regs(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map); +int cxl_await_range_active(struct cxl_dev_state *cxlds); =20 #endif /* __CXL_CXL_H__ */ --=20 2.25.1