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Wed, 11 Mar 2026 12:25:07 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 08/15] irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ and TINT helpers Date: Wed, 11 Mar 2026 19:24:39 +0000 Message-ID: <20260311192459.609064-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das rzfive_tint_irq_endisable() handled both IRQ and TINT enable/disable paths via a hw_irq range check. Split this into two dedicated helpers, rzfive_irq_endisable() for IRQ interrupts and rzfive_tint_endisable() for TINT interrupts, each operating unconditionally on their respective interrupt type. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 78 +++++++++++++++++------------ 1 file changed, 47 insertions(+), 31 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 0d6b72e1bc02..9e0080c5ec95 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -212,48 +212,64 @@ static void rzfive_irqc_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } =20 -static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) +static void rzfive_irq_endisable(struct irq_data *d, bool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { - u32 offset =3D hwirq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(offset); - u8 tssr_index =3D TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - if (enable) - rzfive_irqc_unmask_tint_interrupt(priv, hwirq); - else - rzfive_irqc_mask_tint_interrupt(priv, hwirq); - reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); - if (enable) - reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); - else - reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); - raw_spin_unlock(&priv->lock); - } else { - raw_spin_lock(&priv->lock); - if (enable) - rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else - rzfive_irqc_mask_irq_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); - } + raw_spin_lock(&priv->lock); + if (enable) + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); + else + rzfive_irqc_mask_irq_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); +} + +static void rzfive_tint_endisable(struct irq_data *d, bool enable) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + u32 offset =3D hwirq - IRQC_TINT_START; + u32 tssr_offset =3D TSSR_OFFSET(offset); + u8 tssr_index =3D TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + if (enable) + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); + else + rzfive_irqc_mask_tint_interrupt(priv, hwirq); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + if (enable) + reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); } =20 static void rzfive_irqc_irq_disable(struct irq_data *d) { irq_chip_disable_parent(d); - rzfive_tint_irq_endisable(d, false); + rzfive_irq_endisable(d, false); } =20 static void rzfive_irqc_irq_enable(struct irq_data *d) { - rzfive_tint_irq_endisable(d, true); + rzfive_irq_endisable(d, true); + irq_chip_enable_parent(d); +} + +static void rzfive_irqc_tint_disable(struct irq_data *d) +{ + irq_chip_disable_parent(d); + rzfive_tint_endisable(d, false); +} + +static void rzfive_irqc_tint_enable(struct irq_data *d) +{ + rzfive_tint_endisable(d, true); irq_chip_enable_parent(d); } =20 @@ -504,8 +520,8 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D { .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, - .irq_disable =3D rzfive_irqc_irq_disable, - .irq_enable =3D rzfive_irqc_irq_enable, + .irq_disable =3D rzfive_irqc_tint_disable, + .irq_enable =3D rzfive_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, --=20 2.43.0