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Wed, 11 Mar 2026 12:25:06 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 06/15] irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and TINT functions Date: Wed, 11 Mar 2026 19:24:37 +0000 Message-ID: <20260311192459.609064-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The single rzg2l_irqc_set_type() handler used hw_irq range checks to dispatch to either rzg2l_irq_set_type() or rzg2l_tint_set_edge(). Split this into two dedicated handlers, rzg2l_irqc_irq_set_type() and rzg2l_irqc_tint_set_type(), each calling only their respective type configuration function without runtime conditionals. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 1c5083a48561..c779bcc4028d 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -393,15 +393,22 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) return 0; } =20 -static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) +static int rzg2l_irqc_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq =3D irqd_to_hwirq(d); - int ret =3D -EINVAL; + int ret; + + ret =3D rzg2l_irq_set_type(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static int rzg2l_irqc_tint_set_type(struct irq_data *d, unsigned int type) +{ + int ret; =20 - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) - ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - ret =3D rzg2l_tint_set_edge(d, type); + ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; =20 @@ -454,7 +461,7 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_irq_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -471,7 +478,7 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_tint_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -488,7 +495,7 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_irq_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -505,7 +512,7 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_tint_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | --=20 2.43.0