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Wed, 11 Mar 2026 12:25:13 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 15/15] irqchip/renesas-rzg2l: Add shared interrupt support Date: Wed, 11 Mar 2026 19:24:46 +0000 Message-ID: <20260311192459.609064-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of external interrupts in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external interrupts out of which it shares 8 interrupts with TINT, whereas RZ/G2L has only 8 external interrupts. Add shared_irq variable in struct rzg2l_hw_info to handle these differences by adding the callback irq_{request,release}_resources(). Signed-off-by: Biju Das --- v4->v5: * Added callback irq_{request,release}_resources() to both irq and tint interrupt chips. v3->v4: * Updated commit header irq->interrupt. * Updated commit description IRQs->interrupts. * Updated shared_irq_cnt variable type from u8->unsigned int. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 92 +++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index e4c06e382120..aa65ab379179 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -29,6 +29,8 @@ #define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 +#define INTTSEL 0x2c +#define TINTSEL(n) BIT(n) #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) @@ -58,10 +60,12 @@ /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @iitsr: IITSR register + * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { u32 iitsr; + u32 inttsel; u32 titsr[2]; }; =20 @@ -71,12 +75,14 @@ struct rzg2l_irqc_reg_cache { * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts + * @shared_irq_cnt: Number of shared interrupts */ struct rzg2l_hw_info { const u8 *tssel_lut; unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; + unsigned int shared_irq_cnt; }; =20 /** @@ -333,6 +339,83 @@ static void rzg2l_irqc_tint_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.tint_start - info.shared_irq_cnt)) && hw_irq <= info.tint_start); +} + +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.num_irq - info.shared_irq_cnt)) && hw_irq < in= fo.num_irq); +} + +static int rzg2l_irqc_irq_request_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 offset, tssr_offset; + u8 tssr_index, tssel_shift; + u32 reg, inttsel_reg; + u8 value; + + if (!priv->info.shared_irq_cnt) + return 0; + + if (rzg2l_irqc_is_shared_irqc(priv->info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - priv->info.tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + tssel_shift =3D TSSEL_SHIFT(tssr_offset); + + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + value =3D (reg & (TIEN << tssel_shift)) >> tssel_shift; + if (value) + goto err_conflict; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg |=3D TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } else if (rzg2l_irqc_is_shared_tint(priv->info, hw_irq)) { + offset =3D hw_irq - priv->info.tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + value =3D (inttsel_reg & TINTSEL(offset)) >> offset; + if (value) + goto err_conflict; + } + + return 0; + +err_conflict: + pr_err("%s: Shared SPI conflict!\n", __func__); + return -EBUSY; +} + +static void rzg2l_irqc_irq_release_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 offset; + u8 inttsel_reg; + + if (!priv->info.shared_irq_cnt) + return; + + if (rzg2l_irqc_is_shared_irqc(priv->info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - priv->info.tint_start; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg &=3D ~TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } +} + static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -468,6 +551,8 @@ static int rzg2l_irqc_irq_suspend(void *data) void __iomem *base =3D rzg2l_irqc_data->base; =20 cache->iitsr =3D readl_relaxed(base + IITSR); + if (rzg2l_irqc_data->info.shared_irq_cnt) + cache->inttsel =3D readl_relaxed(base + INTTSEL); for (u8 i =3D 0; i < 2; i++) cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); =20 @@ -486,6 +571,8 @@ static void rzg2l_irqc_irq_resume(void *data) */ for (u8 i =3D 0; i < 2; i++) writel_relaxed(cache->titsr[i], base + TITSR(i)); + if (rzg2l_irqc_data->info.shared_irq_cnt) + writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); } =20 @@ -505,6 +592,8 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D irq_chip_disable_parent, .irq_enable =3D irq_chip_enable_parent, + .irq_request_resources =3D rzg2l_irqc_irq_request_resources, + .irq_release_resources =3D rzg2l_irqc_irq_release_resources, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -522,6 +611,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_tint_disable, .irq_enable =3D rzg2l_irqc_tint_enable, + .irq_request_resources =3D rzg2l_irqc_irq_request_resources, + .irq_release_resources =3D rzg2l_irqc_irq_release_resources, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -722,6 +813,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params =3D { .irq_count =3D 16, .tint_start =3D IRQC_IRQ_START + 16, .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, + .shared_irq_cnt =3D 8, }; =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { --=20 2.43.0