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Wed, 11 Mar 2026 12:25:02 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 01/15] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Date: Wed, 11 Mar 2026 19:24:32 +0000 Message-ID: <20260311192459.609064-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Simplify the bindings by using pattern property for interrupt-names. It also allows to change the ordering of interrupts. Signed-off-by: Biju Das Reviewed-by: Rob Herring (Arm) --- v4->v5: * No change. v3->v4: * Updated commit description. v2->v3: [3] * Dropped items and instead used enum for single compatible values * Add minItems for interrupts and interrupt-names properties of=20 the RZ/{G2L,G2UL,Five,V2L} SoCs * Replaced maxItems->minItems for interrupts and interrupt-names properties of the RZ/G3L SoC. v1->v2: [2] * Simplified the binding using pattern [3] https://lore.kernel.org/all/20260204180632.249139-3-biju.das.jz@bp.rene= sas.com/ [2] https://lore.kernel.org/all/20260206111658.231934-3-biju.das.jz@bp.rene= sas.com/ [1]https://lore.kernel.org/all/20260204142320.103184-2-biju.das.jz@bp.renes= as.com/ --- v3->v4: * Collected tag from Rob [1] * Updated commit description and kept the tag as it is trivial change. v2->v3: [2] * No change v1->v2: * New patch [1]. [1] https://lore.kernel.org/all/20260204180632.249139-2-biju.das.jz@bp.rene= sas.com/ [2] https://lore.kernel.org/all/20260206111658.231934-2-biju.das.jz@bp.rene= sas.com/ --- .../renesas,rzg2l-irqc.yaml | 120 ++++-------------- 1 file changed, 23 insertions(+), 97 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml index 44b6ae5fc802..a0b57d808639 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -48,107 +48,33 @@ properties: =20 interrupts: minItems: 45 - items: - - description: NMI interrupt - - description: IRQ0 interrupt - - description: IRQ1 interrupt - - description: IRQ2 interrupt - - description: IRQ3 interrupt - - description: IRQ4 interrupt - - description: IRQ5 interrupt - - description: IRQ6 interrupt - - description: IRQ7 interrupt - - description: GPIO interrupt, TINT0 - - description: GPIO interrupt, TINT1 - - description: GPIO interrupt, TINT2 - - description: GPIO interrupt, TINT3 - - description: GPIO interrupt, TINT4 - - description: GPIO interrupt, TINT5 - - description: GPIO interrupt, TINT6 - - description: GPIO interrupt, TINT7 - - description: GPIO interrupt, TINT8 - - description: GPIO interrupt, TINT9 - - description: GPIO interrupt, TINT10 - - description: GPIO interrupt, TINT11 - - description: GPIO interrupt, TINT12 - - description: GPIO interrupt, TINT13 - - description: GPIO interrupt, TINT14 - - description: GPIO interrupt, TINT15 - - description: GPIO interrupt, TINT16 - - description: GPIO interrupt, TINT17 - - description: GPIO interrupt, TINT18 - - description: GPIO interrupt, TINT19 - - description: GPIO interrupt, TINT20 - - description: GPIO interrupt, TINT21 - - description: GPIO interrupt, TINT22 - - description: GPIO interrupt, TINT23 - - description: GPIO interrupt, TINT24 - - description: GPIO interrupt, TINT25 - - description: GPIO interrupt, TINT26 - - description: GPIO interrupt, TINT27 - - description: GPIO interrupt, TINT28 - - description: GPIO interrupt, TINT29 - - description: GPIO interrupt, TINT30 - - description: GPIO interrupt, TINT31 - - description: Bus error interrupt - - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt - - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt - - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt - - description: ECCRAM1 1bit error interrupt - - description: ECCRAM1 2bit error interrupt - - description: ECCRAM1 error overflow interrupt + maxItems: 48 =20 interrupt-names: minItems: 45 + maxItems: 48 items: - - const: nmi - - const: irq0 - - const: irq1 - - const: irq2 - - const: irq3 - - const: irq4 - - const: irq5 - - const: irq6 - - const: irq7 - - const: tint0 - - const: tint1 - - const: tint2 - - const: tint3 - - const: tint4 - - const: tint5 - - const: tint6 - - const: tint7 - - const: tint8 - - const: tint9 - - const: tint10 - - const: tint11 - - const: tint12 - - const: tint13 - - const: tint14 - - const: tint15 - - const: tint16 - - const: tint17 - - const: tint18 - - const: tint19 - - const: tint20 - - const: tint21 - - const: tint22 - - const: tint23 - - const: tint24 - - const: tint25 - - const: tint26 - - const: tint27 - - const: tint28 - - const: tint29 - - const: tint30 - - const: tint31 - - const: bus-err - - const: ec7tie1-0 - - const: ec7tie2-0 - - const: ec7tiovf-0 - - const: ec7tie1-1 - - const: ec7tie2-1 - - const: ec7tiovf-1 + oneOf: + - description: NMI interrupt + const: nmi + - description: External IRQ interrupt + pattern: '^irq([0-7])$' + - description: GPIO interrupt + pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$' + - description: Bus error interrupt + const: bus-err + - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt + const: ec7tie1-0 + - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt + const: ec7tie2-0 + - description: ECCRAM0 or combined ECCRAM0/1 error overflow interr= upt + const: ec7tiovf-0 + - description: ECCRAM1 1bit error interrupt + const: ec7tie1-1 + - description: ECCRAM1 2bit error interrupt + const: ec7tie2-1 + - description: ECCRAM1 error overflow interrupt + const: ec7tiovf-1 =20 clocks: maxItems: 2 --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AB9A3358DA for ; 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charset="utf-8" From: Biju Das Document RZ/G3L (R9A08G046) IRQC. The IRQC block on the RZ/G3L SoC is nearly identical to that found on the RZ/G3S SoC, with the following differences: it supports more external interrupts and GPT error interrupts, and adds registers for GPT/MTU interrupt selection and shared interrupt selection between external interrupt and TINT. A new compatible string "renesas,r9a08g046-irqc" is therefore introduced for the RZ/G3L SoC. Signed-off-by: Biju Das Reviewed-by: Rob Herring (Arm) --- v4->v5: * No change. v3->v4: [4] * Updated commit description. v2->v3: [3] * Dropped items and instead used enum for single compatible values * Add minItems for interrupts and interrupt-names properties of=20 the RZ/{G2L,G2UL,Five,V2L} SoCs * Replaced maxItems->minItems for interrupts and interrupt-names properties of the RZ/G3L SoC. v1->v2: [2] * Simplified the binding using pattern [4] https://lore.kernel.org/all/20260227140316.308106-3-biju.das.jz@bp.rene= sas.com/ [3] https://lore.kernel.org/all/20260204180632.249139-3-biju.das.jz@bp.rene= sas.com/ [2] https://lore.kernel.org/all/20260206111658.231934-3-biju.das.jz@bp.rene= sas.com/ [1]https://lore.kernel.org/all/20260204142320.103184-2-biju.das.jz@bp.renes= as.com/ --- .../renesas,rzg2l-irqc.yaml | 43 ++++++++++++++++--- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml index a0b57d808639..3a221e1800a0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -30,7 +30,9 @@ properties: - renesas,r9a08g045-irqc # RZ/G3S - const: renesas,rzg2l-irqc =20 - - const: renesas,r9a07g043f-irqc # RZ/Five + - enum: + - renesas,r9a07g043f-irqc # RZ/Five + - renesas,r9a08g046-irqc # RZ/G3L =20 '#interrupt-cells': description: The first cell should contain a macro RZG2L_{NMI,IRQX} in= cluded in the @@ -48,17 +50,17 @@ properties: =20 interrupts: minItems: 45 - maxItems: 48 + maxItems: 61 =20 interrupt-names: minItems: 45 - maxItems: 48 + maxItems: 61 items: oneOf: - description: NMI interrupt const: nmi - description: External IRQ interrupt - pattern: '^irq([0-7])$' + pattern: '^irq([0-9]|1[0-5])$' - description: GPIO interrupt pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$' - description: Bus error interrupt @@ -75,6 +77,8 @@ properties: const: ec7tie2-1 - description: ECCRAM1 error overflow interrupt const: ec7tiovf-1 + - description: Integrated GPT Error interrupt + pattern: '^ovfunf([0-7])$' =20 clocks: maxItems: 2 @@ -106,6 +110,24 @@ required: allOf: - $ref: /schemas/interrupt-controller.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043f-irqc + - renesas,r9a07g043u-irqc + - renesas,r9a07g044-irqc + - renesas,r9a07g054-irqc + then: + properties: + interrupts: + minItems: 48 + maxItems: 48 + interrupt-names: + minItems: 48 + maxItems: 48 + - if: properties: compatible: @@ -118,12 +140,19 @@ allOf: maxItems: 45 interrupt-names: maxItems: 45 - else: + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a08g046-irqc + then: properties: interrupts: - minItems: 48 + minItems: 61 interrupt-names: - minItems: 48 + minItems: 61 =20 unevaluatedProperties: false =20 --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1CEC322B96 for ; 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charset="utf-8" From: Biju Das The check `hwirq < IRQC_TINT_START` in rzg2l_irqc_alloc() is unnecessary as the condition is already guaranteed to be false at that point in the code. The outer `if (hwirq > IRQC_IRQ_COUNT)` block ensures that hwirq is always above IRQC_IRQ_COUNT before reaching this check, and since IRQC_TINT_START <=3D IRQC_IRQ_COUNT, the guard can never trigger. Remove the dead code to simplify the allocation path. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index e73d426cea6d..ed8044b0a339 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -491,9 +491,6 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, if (hwirq > IRQC_IRQ_COUNT) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); - - if (hwirq < IRQC_TINT_START) - return -EINVAL; } =20 if (hwirq > (IRQC_NUM_IRQ - 1)) --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BED6632C316 for ; Wed, 11 Mar 2026 19:25:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 11 Mar 2026 12:25:05 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:38b7:8ca3:cb55:d344]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439fe20bd9csm1323210f8f.21.2026.03.11.12.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 12:25:04 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 04/15] irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances Date: Wed, 11 Mar 2026 19:24:35 +0000 Message-ID: <20260311192459.609064-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The driver previously used a single irq_chip instance shared across all interrupt types, relying on dispatcher callbacks to differentiate between IRQ and TINT regions at runtime. Replace the per-SoC irq_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: IRQ and TINT. Subsequent patches will add per-region callbacks for IRQ and TINT from the common code. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 61 ++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index ed8044b0a339..a0f03f81d5ef 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -71,14 +71,16 @@ struct rzg2l_irqc_reg_cache { /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip + * @irq_chip: Pointer to struct irq_chip for irq + * @tint_chip: Pointer to struct irq_chip for tint * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; - const struct irq_chip *irqchip; + const struct irq_chip *irq_chip; + const struct irq_chip *tint_chip; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -434,7 +436,7 @@ static struct syscore rzg2l_irqc_syscore =3D { .ops =3D &rzg2l_irqc_syscore_ops, }; =20 -static const struct irq_chip rzg2l_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D irq_chip_mask_parent, @@ -451,7 +453,41 @@ static const struct irq_chip rzg2l_irqc_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 -static const struct irq_chip rzfive_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_tint_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzg2l_irqc_irq_disable, + .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_irq_chip =3D { + .name =3D "rzfive-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D rzfive_irqc_mask, + .irq_unmask =3D rzfive_irqc_unmask, + .irq_disable =3D rzfive_irqc_irq_disable, + .irq_enable =3D rzfive_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D rzfive_irqc_mask, @@ -472,6 +508,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, unsigned int nr_irqs, void *arg) { struct rzg2l_irqc_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -491,13 +528,15 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain= , unsigned int virq, if (hwirq > IRQC_IRQ_COUNT) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); + chip =3D priv->tint_chip; + } else { + chip =3D priv->irq_chip; } =20 if (hwirq > (IRQC_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20 @@ -529,7 +568,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, } =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, - const struct irq_chip *irq_chip) + const struct irq_chip *irq_chip, + const struct irq_chip *tint_chip) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -545,7 +585,8 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (!rzg2l_irqc_data) return -ENOMEM; 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charset="utf-8" From: Biju Das The single rzg2l_irqc_eoi() handler used a conditional to determine whether to clear an IRQ or TINT interrupt. Split this into two dedicated handlers, rzg2l_irqc_irq_eoi() and rzg2l_irqc_tint_eoi(), each handling only their respective interrupt type without the need for range checks. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index a0f03f81d5ef..1c5083a48561 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -130,16 +130,24 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_pr= iv *priv, unsigned int hwir } } =20 -static void rzg2l_irqc_eoi(struct irq_data *d) +static void rzg2l_irqc_irq_eoi(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 raw_spin_lock(&priv->lock); - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) - rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - rzg2l_clear_tint_int(priv, hw_irq); + rzg2l_clear_irq_int(priv, hw_irq); + raw_spin_unlock(&priv->lock); + irq_chip_eoi_parent(d); +} + +static void rzg2l_irqc_tint_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); } @@ -438,7 +446,7 @@ static struct syscore rzg2l_irqc_syscore =3D { =20 static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, @@ -455,7 +463,7 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { =20 static const struct irq_chip rzg2l_irqc_tint_chip =3D { .name =3D "rzg2l-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, @@ -472,7 +480,7 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { =20 static const struct irq_chip rzfive_irqc_irq_chip =3D { .name =3D "rzfive-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, .irq_disable =3D rzfive_irqc_irq_disable, @@ -489,7 +497,7 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { =20 static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, .irq_disable =3D rzfive_irqc_irq_disable, --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AD81376BFF for ; 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charset="utf-8" From: Biju Das The single rzg2l_irqc_set_type() handler used hw_irq range checks to dispatch to either rzg2l_irq_set_type() or rzg2l_tint_set_edge(). Split this into two dedicated handlers, rzg2l_irqc_irq_set_type() and rzg2l_irqc_tint_set_type(), each calling only their respective type configuration function without runtime conditionals. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 1c5083a48561..c779bcc4028d 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -393,15 +393,22 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) return 0; } =20 -static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) +static int rzg2l_irqc_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq =3D irqd_to_hwirq(d); - int ret =3D -EINVAL; + int ret; + + ret =3D rzg2l_irq_set_type(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static int rzg2l_irqc_tint_set_type(struct irq_data *d, unsigned int type) +{ + int ret; =20 - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) - ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - ret =3D rzg2l_tint_set_edge(d, type); + ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; =20 @@ -454,7 +461,7 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_irq_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -471,7 +478,7 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_tint_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -488,7 +495,7 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_irq_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -505,7 +512,7 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_tint_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EF83C9441 for ; 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charset="utf-8" From: Biju Das rzg2l_irqc_irq_disable() and rzg2l_irqc_irq_enable() were used by both the IRQ and TINT chips, but only performed TINT-specific work via rzg2l_tint_irq_endisable(), guarded by a hw_irq range check. Since the IRQ chip does not require this extra enable/disable handling, replace its callbacks with the generic irq_chip_disable_parent() and irq_chip_enable_parent() directly. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 41 +++++++++++++---------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index c779bcc4028d..0d6b72e1bc02 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -259,33 +259,30 @@ static void rzfive_irqc_irq_enable(struct irq_data *d) =20 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); + u32 offset =3D hw_irq - IRQC_TINT_START; + u32 tssr_offset =3D TSSR_OFFSET(offset); + u8 tssr_index =3D TSSR_INDEX(offset); + u32 reg; =20 - if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); - u32 offset =3D hw_irq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(offset); - u8 tssr_index =3D TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); - if (enable) - reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); - else - reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); - raw_spin_unlock(&priv->lock); - } + raw_spin_lock(&priv->lock); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + if (enable) + reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); } =20 -static void rzg2l_irqc_irq_disable(struct irq_data *d) +static void rzg2l_irqc_tint_disable(struct irq_data *d) { irq_chip_disable_parent(d); rzg2l_tint_irq_endisable(d, false); } =20 -static void rzg2l_irqc_irq_enable(struct irq_data *d) +static void rzg2l_irqc_tint_enable(struct irq_data *d) { rzg2l_tint_irq_endisable(d, true); irq_chip_enable_parent(d); @@ -456,8 +453,8 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzg2l_irqc_irq_disable, - .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -473,8 +470,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzg2l_irqc_irq_disable, - .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_disable =3D rzg2l_irqc_tint_disable, + .irq_enable =3D rzg2l_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B39E13D9024 for ; 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charset="utf-8" From: Biju Das rzfive_tint_irq_endisable() handled both IRQ and TINT enable/disable paths via a hw_irq range check. Split this into two dedicated helpers, rzfive_irq_endisable() for IRQ interrupts and rzfive_tint_endisable() for TINT interrupts, each operating unconditionally on their respective interrupt type. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 78 +++++++++++++++++------------ 1 file changed, 47 insertions(+), 31 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 0d6b72e1bc02..9e0080c5ec95 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -212,48 +212,64 @@ static void rzfive_irqc_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } =20 -static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) +static void rzfive_irq_endisable(struct irq_data *d, bool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { - u32 offset =3D hwirq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(offset); - u8 tssr_index =3D TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - if (enable) - rzfive_irqc_unmask_tint_interrupt(priv, hwirq); - else - rzfive_irqc_mask_tint_interrupt(priv, hwirq); - reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); - if (enable) - reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); - else - reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); - raw_spin_unlock(&priv->lock); - } else { - raw_spin_lock(&priv->lock); - if (enable) - rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else - rzfive_irqc_mask_irq_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); - } + raw_spin_lock(&priv->lock); + if (enable) + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); + else + rzfive_irqc_mask_irq_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); +} + +static void rzfive_tint_endisable(struct irq_data *d, bool enable) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + u32 offset =3D hwirq - IRQC_TINT_START; + u32 tssr_offset =3D TSSR_OFFSET(offset); + u8 tssr_index =3D TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + if (enable) + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); + else + rzfive_irqc_mask_tint_interrupt(priv, hwirq); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + if (enable) + reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); } =20 static void rzfive_irqc_irq_disable(struct irq_data *d) { irq_chip_disable_parent(d); - rzfive_tint_irq_endisable(d, false); + rzfive_irq_endisable(d, false); } =20 static void rzfive_irqc_irq_enable(struct irq_data *d) { - rzfive_tint_irq_endisable(d, true); + rzfive_irq_endisable(d, true); + irq_chip_enable_parent(d); +} + +static void rzfive_irqc_tint_disable(struct irq_data *d) +{ + irq_chip_disable_parent(d); + rzfive_tint_endisable(d, false); +} + +static void rzfive_irqc_tint_enable(struct irq_data *d) +{ + rzfive_tint_endisable(d, true); irq_chip_enable_parent(d); } =20 @@ -504,8 +520,8 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D { .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, - .irq_disable =3D rzfive_irqc_irq_disable, - .irq_enable =3D rzfive_irqc_irq_enable, + .irq_disable =3D rzfive_irqc_tint_disable, + .irq_enable =3D rzfive_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CAA73E5590 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das rzfive_irqc_mask() and rzfive_irqc_unmask() used hw_irq range checks to dispatch between IRQ and TINT masking operations. Split each into two dedicated handlers =E2=80=94 rzfive_irqc_irq_mask(), rzfive_irqc_tint_mask(= ), rzfive_irqc_irq_unmask(), and rzfive_irqc_tint_unmask() =E2=80=94 each operating unconditionally on their respective interrupt type, removing the runtime conditionals. Assign the IRQ-specific handlers to rzfive_irqc_irq_chip and the TINT-specific handlers to rzfive_irqc_tint_chip, consistent with the separation applied to the EOI, set_type, and enable/disable callbacks in previous patches. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 44 ++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 9e0080c5ec95..fd017c73dfc5 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -184,30 +184,46 @@ static void rzfive_irqc_unmask_tint_interrupt(struct = rzg2l_irqc_priv *priv, writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } =20 -static void rzfive_irqc_mask(struct irq_data *d) +static void rzfive_irqc_irq_mask(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) - rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) - rzfive_irqc_mask_tint_interrupt(priv, hwirq); + rzfive_irqc_mask_irq_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_mask_parent(d); } =20 -static void rzfive_irqc_unmask(struct irq_data *d) +static void rzfive_irqc_tint_mask(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) - rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) - rzfive_irqc_unmask_tint_interrupt(priv, hwirq); + rzfive_irqc_mask_tint_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); + irq_chip_mask_parent(d); +} + +static void rzfive_irqc_irq_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); + irq_chip_unmask_parent(d); +} + +static void rzfive_irqc_tint_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_unmask_parent(d); } @@ -501,8 +517,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { static const struct irq_chip rzfive_irqc_irq_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_irq_eoi, - .irq_mask =3D rzfive_irqc_mask, - .irq_unmask =3D rzfive_irqc_unmask, + .irq_mask =3D rzfive_irqc_irq_mask, + .irq_unmask =3D rzfive_irqc_irq_unmask, .irq_disable =3D rzfive_irqc_irq_disable, .irq_enable =3D rzfive_irqc_irq_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, @@ -518,8 +534,8 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_tint_eoi, - .irq_mask =3D rzfive_irqc_mask, - .irq_unmask =3D rzfive_irqc_unmask, + .irq_mask =3D rzfive_irqc_tint_mask, + .irq_unmask =3D rzfive_irqc_tint_unmask, .irq_disable =3D rzfive_irqc_tint_disable, .irq_enable =3D rzfive_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D47F3375F68 for ; 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charset="utf-8" From: Biju Das The total number of interrupts in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external interrupts whereas RZ/G2L has only 8 external interrupts. Dynamically allocate fwspec memory instead of static allocation to support both SoCs. Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Updated commit header * Replaced IRQs->interrupts in commit description * Fixed the typo Dynamicaly->Dynamically v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index fd017c73dfc5..cd850c7dc6f3 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -81,7 +81,7 @@ static struct rzg2l_irqc_priv { void __iomem *base; const struct irq_chip *irq_chip; const struct irq_chip *tint_chip; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + struct irq_fwspec *fwspec; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; } *rzg2l_irqc_data; @@ -636,6 +636,11 @@ static int rzg2l_irqc_common_probe(struct platform_dev= ice *pdev, struct device_n if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); =20 + rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ, + sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL); 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Wed, 11 Mar 2026 12:25:10 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 11/15] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro Date: Wed, 11 Mar 2026 19:24:42 +0000 Message-ID: <20260311192459.609064-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of interrupts in RZ/G2L and RZ/G3L SoC are different. Introduce struct rzg2l_hw_info to handle the hardware differences and replace the macro IRQC_NUM_IRQ with num_irq variable in struct rzg2l_hw_info. Signed-off-by: Biju Das --- v4->v5: * Dropped the hw_irq range check involving info.num_irq v3->v4: * Updated commit description IRQs->interrupts * Replaced the variable type for num_irq in struct rzg2l_hw_info from u8->unsigned int * Replaced the pointer variable info from irqc_priv and instead embed a struct hwinfo into irqc_priv and copy the data into it at probe time. * Replaced the check 'hwirq > (priv->info->num_irq - 1)' with hwirq >=3D priv->info.num_irq v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 34 ++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index cd850c7dc6f3..11fff8fdf4b3 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -24,7 +24,6 @@ #define IRQC_IRQ_COUNT 8 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) =20 #define ISCR 0x10 #define IITSR 0x14 @@ -68,6 +67,14 @@ struct rzg2l_irqc_reg_cache { u32 titsr[2]; }; =20 +/** + * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @num_irq: Total Number of interrupts + */ +struct rzg2l_hw_info { + unsigned int num_irq; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address @@ -75,6 +82,7 @@ struct rzg2l_irqc_reg_cache { * @tint_chip: Pointer to struct irq_chip for tint * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Hardware specific data * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { @@ -83,6 +91,7 @@ static struct rzg2l_irqc_priv { const struct irq_chip *tint_chip; struct irq_fwspec *fwspec; raw_spinlock_t lock; + struct rzg2l_hw_info info; struct rzg2l_irqc_reg_cache cache; } *rzg2l_irqc_data; =20 @@ -577,7 +586,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, chip =3D priv->irq_chip; } =20 - if (hwirq > (IRQC_NUM_IRQ - 1)) + if (hwirq >=3D priv->info.num_irq) return -EINVAL; =20 ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); @@ -600,7 +609,7 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, unsigned int i; int ret; =20 - for (i =3D 0; i < IRQC_NUM_IRQ; i++) { + for (i =3D 0; i < priv->info.num_irq; i++) { ret =3D of_irq_parse_one(np, i, &map); if (ret) return ret; @@ -613,7 +622,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, const struct irq_chip *irq_chip, - const struct irq_chip *tint_chip) + const struct irq_chip *tint_chip, + const struct rzg2l_hw_info info) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -636,7 +646,9 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); =20 - rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ, + rzg2l_irqc_data->info =3D info; + + rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, info.num_irq, sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL); if (!rzg2l_irqc_data->fwspec) return -ENOMEM; @@ -661,7 +673,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n =20 raw_spin_lock_init(&rzg2l_irqc_data->lock); =20 - irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, IRQC_NUM_IRQ= , dev_fwnode(dev), + irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, info.num_irq= , dev_fwnode(dev), &rzg2l_irqc_domain_ops, rzg2l_irqc_data); if (!irq_domain) { pm_runtime_put(dev); @@ -673,14 +685,20 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n return 0; } =20 +static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, +}; + static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip, + rzg2l_hw_params); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip, + rzg2l_hw_params); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) --=20 2.43.0 From nobody Tue Apr 7 19:50:35 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B44823EAC9A for ; Wed, 11 Mar 2026 19:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773257115; cv=none; b=H8uQA0QmVZI5Ri/dwD1CFYWG/6VyQ2ZJKScbSIMhCN7qVU6rCGOYMhroTfnu/gkMdHCfMPtMQocWNhLesA3c1gSDhGbOMiaRrFhqsOh2UXSj42gi5qTUaeQ6I3aaceSgUZphLM+6jiD8xDXQ2+KKinFuIWqlg+agcG3To+traZw= ARC-Message-Signature: i=1; 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charset="utf-8" From: Biju Das The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add tint_start variable in struct rzg2l_hw_info to handle this difference and drop the macro IRQC_TINT_START. Signed-off-by: Biju Das --- v4->v5: * Dropped the hw_irq nage check involving info.tint_start v3->v4: * Updated commit description 'this differences->this difference'. * Updated tint_start variable type from u8-> unsigned int. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 11fff8fdf4b3..ca495fb0d1ae 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,7 +22,6 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 -#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + unsigned int tint_start; unsigned int num_irq; }; =20 @@ -125,7 +126,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv = *priv, unsigned int hwirq =20 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned in= t hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); u32 reg; =20 reg =3D readl_relaxed(priv->base + TSCR); @@ -180,7 +181,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg= 2l_irqc_priv *priv, static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK); } @@ -188,7 +189,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2= l_irqc_priv *priv, static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } @@ -255,7 +256,7 @@ static void rzfive_tint_endisable(struct irq_data *d, b= ool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - u32 offset =3D hwirq - IRQC_TINT_START; + u32 offset =3D hwirq - priv->info.tint_start; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -302,7 +303,7 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d= , bool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); - u32 offset =3D hw_irq - IRQC_TINT_START; + u32 offset =3D hw_irq - priv->info.tint_start; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -392,7 +393,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsi= gned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); 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charset="utf-8" From: Biju Das The total number of external interrupts in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external interrupts whereas RZ/G2L has only 8 external interrupts. Add irq_count variable in struct rzg2l_hw_info to handle these differences and drop the macro IRQC_IRQ_COUNT. Signed-off-by: Biju Das --- v4->v5: * Dropped hw_irq range check involving info.irq_count. v3->v4: * Updated commit description IRQs->interrupts. * Updated variable type of irq_count from u8->unsigned int. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index ca495fb0d1ae..78744c21b45a 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -21,7 +21,6 @@ #include =20 #define IRQC_IRQ_START 1 -#define IRQC_IRQ_COUNT 8 #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -68,10 +67,12 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; }; @@ -579,7 +580,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, * from 16-31 bits. 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charset="utf-8" From: Biju Das The IRQC block on the RZ/G3L SoC is almost identical to the one found on the RZ/G2L SoC, with the following differences: - The number of GPIO interrupts for TINT selection is 113 instead of 123. - The pin index and TINT selection index are not in the 1:1 map. - The number of external interrupts are 16 instead of 8, out of these 8 external interrupts are shared with TINT. Add support for the RZ/G3L driver by filling the rzg2l_hw_info table and adding LUT for mapping between pin index and TINT selection index. Signed-off-by: Biju Das --- v4->v5: * Updated rzg3l_irqc_probe() for supporting separate interrupt chips. v3->v4: * Updated commit description IRQs->interrupts. * Updated rzg2l_disable_tint_and_set_tint_source() for making tint assignment very clear in the code. * Formatted rzg3l_tssel_lut as table format. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 44 +++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 78744c21b45a..e4c06e382120 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -67,11 +67,13 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tssel_lut: TINT lookup table * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + const u8 *tssel_lut; unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; @@ -381,6 +383,11 @@ static u32 rzg2l_disable_tint_and_set_tint_source(stru= ct irq_data *d, struct rzg u32 tint =3D (u32)(uintptr_t)irq_data_get_irq_chip_data(d); u32 tien =3D reg & (TIEN << TSSEL_SHIFT(tssr_offset)); =20 + if (priv->info.tssel_lut) + tint =3D priv->info.tssel_lut[tint]; + else + tint =3D (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + /* Clear the relevant byte in reg */ reg &=3D ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); /* Set TINT and leave TIEN clear */ @@ -687,6 +694,36 @@ static int rzg2l_irqc_common_probe(struct platform_dev= ice *pdev, struct device_n return 0; } =20 +/* Mapping based on port index on Table 4.2-1 and GPIOINT on Table 4.6-7 */ +static const u8 rzg3l_tssel_lut[] =3D { + 83, 84, /* P20-P21 */ + 7, 8, 9, 10, 11, 12, 13, /* P30-P36 */ + 85, 86, 87, 88, 89, 90, 91, /* P50-P56 */ + 92, 93, 94, 95, 96, 97, 98, /* P60-P66 */ + 99, 100, 101, 102, 103, 104, 105, 106, /* P70-P77 */ + 107, 108, 109, 110, 111, 112, /* P80-P85 */ + 45, 46, 47, 48, 49, 50, 51, 52, /* PA0-PA7 */ + 53, 54, 55, 56, 57, 58, 59, 60, /* PB0-PB7 */ + 61, 62, 63, /* PC0-PC2 */ + 64, 65, 66, 67, 68, 69, 70, 71, /* PD0-PD7 */ + 72, 73, 74, 75, 76, 77, 78, 79, /* PE0-PE7 */ + 80, 81, 82, /* PF0-PF2 */ + 27, 28, 29, 30, 31, 32, 33, 34, /* PG0-PG7 */ + 35, 36, 37, 38, 39, 40, /* PH0-PH5 */ + 2, 3, 4, 5, 6, /* PJ0-PJ4 */ + 41, 42, 43, 44, /* PK0-PK3 */ + 14, 15, 16, 17, 26, /* PL0-PL4 */ + 18, 19, 20, 21, 22, 23, 24, 25, /* PM0-PM7 */ + 0, 1 /* PS0-PS1 */ +}; + +static const struct rzg2l_hw_info rzg3l_hw_params =3D { + .tssel_lut =3D rzg3l_tssel_lut, + .irq_count =3D 16, + .tint_start =3D IRQC_IRQ_START + 16, + .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, +}; + static const struct rzg2l_hw_info rzg2l_hw_params =3D { .irq_count =3D 8, .tint_start =3D IRQC_IRQ_START + 8, @@ -699,6 +736,12 @@ static int rzg2l_irqc_probe(struct platform_device *pd= ev, struct device_node *pa rzg2l_hw_params); } =20 +static int rzg3l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) +{ + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip, + rzg3l_hw_params); +} + static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip, @@ -707,6 +750,7 @@ static int rzfive_irqc_probe(struct platform_device *pd= ev, struct device_node *p =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_probe) +IRQCHIP_MATCH("renesas,r9a08g046-irqc", rzg3l_irqc_probe) IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_probe) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar "); 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Wed, 11 Mar 2026 12:25:13 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 15/15] irqchip/renesas-rzg2l: Add shared interrupt support Date: Wed, 11 Mar 2026 19:24:46 +0000 Message-ID: <20260311192459.609064-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> References: <20260311192459.609064-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of external interrupts in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external interrupts out of which it shares 8 interrupts with TINT, whereas RZ/G2L has only 8 external interrupts. Add shared_irq variable in struct rzg2l_hw_info to handle these differences by adding the callback irq_{request,release}_resources(). Signed-off-by: Biju Das --- v4->v5: * Added callback irq_{request,release}_resources() to both irq and tint interrupt chips. v3->v4: * Updated commit header irq->interrupt. * Updated commit description IRQs->interrupts. * Updated shared_irq_cnt variable type from u8->unsigned int. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 92 +++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index e4c06e382120..aa65ab379179 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -29,6 +29,8 @@ #define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 +#define INTTSEL 0x2c +#define TINTSEL(n) BIT(n) #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) @@ -58,10 +60,12 @@ /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @iitsr: IITSR register + * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { u32 iitsr; + u32 inttsel; u32 titsr[2]; }; =20 @@ -71,12 +75,14 @@ struct rzg2l_irqc_reg_cache { * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts + * @shared_irq_cnt: Number of shared interrupts */ struct rzg2l_hw_info { const u8 *tssel_lut; unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; + unsigned int shared_irq_cnt; }; =20 /** @@ -333,6 +339,83 @@ static void rzg2l_irqc_tint_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.tint_start - info.shared_irq_cnt)) && hw_irq <= info.tint_start); +} + +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.num_irq - info.shared_irq_cnt)) && hw_irq < in= fo.num_irq); +} + +static int rzg2l_irqc_irq_request_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 offset, tssr_offset; + u8 tssr_index, tssel_shift; + u32 reg, inttsel_reg; + u8 value; + + if (!priv->info.shared_irq_cnt) + return 0; + + if (rzg2l_irqc_is_shared_irqc(priv->info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - priv->info.tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + tssel_shift =3D TSSEL_SHIFT(tssr_offset); + + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + value =3D (reg & (TIEN << tssel_shift)) >> tssel_shift; + if (value) + goto err_conflict; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg |=3D TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } else if (rzg2l_irqc_is_shared_tint(priv->info, hw_irq)) { + offset =3D hw_irq - priv->info.tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + value =3D (inttsel_reg & TINTSEL(offset)) >> offset; + if (value) + goto err_conflict; + } + + return 0; + +err_conflict: + pr_err("%s: Shared SPI conflict!\n", __func__); + return -EBUSY; +} + +static void rzg2l_irqc_irq_release_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 offset; + u8 inttsel_reg; + + if (!priv->info.shared_irq_cnt) + return; + + if (rzg2l_irqc_is_shared_irqc(priv->info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - priv->info.tint_start; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg &=3D ~TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } +} + static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -468,6 +551,8 @@ static int rzg2l_irqc_irq_suspend(void *data) void __iomem *base =3D rzg2l_irqc_data->base; =20 cache->iitsr =3D readl_relaxed(base + IITSR); + if (rzg2l_irqc_data->info.shared_irq_cnt) + cache->inttsel =3D readl_relaxed(base + INTTSEL); for (u8 i =3D 0; i < 2; i++) cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); =20 @@ -486,6 +571,8 @@ static void rzg2l_irqc_irq_resume(void *data) */ for (u8 i =3D 0; i < 2; i++) writel_relaxed(cache->titsr[i], base + TITSR(i)); + if (rzg2l_irqc_data->info.shared_irq_cnt) + writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); } =20 @@ -505,6 +592,8 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D irq_chip_disable_parent, .irq_enable =3D irq_chip_enable_parent, + .irq_request_resources =3D rzg2l_irqc_irq_request_resources, + .irq_release_resources =3D rzg2l_irqc_irq_release_resources, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -522,6 +611,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_tint_disable, .irq_enable =3D rzg2l_irqc_tint_enable, + .irq_request_resources =3D rzg2l_irqc_irq_request_resources, + .irq_release_resources =3D rzg2l_irqc_irq_release_resources, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -722,6 +813,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params =3D { .irq_count =3D 16, .tint_start =3D IRQC_IRQ_START + 16, .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, + .shared_irq_cnt =3D 8, }; =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { --=20 2.43.0