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charset="utf-8" To allow this, do the SNP check in spectre_v2_select_mitigation() processing instead of the original commit's implementation in cpu_set_bug_bits(). Since SPECTRE_V2_CMD_AUTO logic falls through to SPECTRE_V2_CMD_FORCE, double-check if SPECTRE_V2_CMD_FORCE is used before allowing SPECTRE_V2_EIBRS with SNP enabled. Also mute SPECTRE_V2_IBRS_PERF_MSG if SNP is enabled on an AutoIBRS capable machine, since, in that case, the message doesn't apply. Fixes: acaa4b5c4c85 ("x86/speculation: Do not enable Automatic IBRS if SEV-= SNP is enabled") Reported-by: Tom Lendacky Cc: Borislav Petkov (AMD) Cc: stable@kernel.org Signed-off-by: Kim Phillips --- v2: - Address Dave Hansen's comment to adhere to using the IBRS_ENHANCED Intel feature flag also for AutoIBRS. v1: https://lore.kernel.org/kvm/20260224180157.725159-2-kim.phillips@amd.com/ arch/x86/kernel/cpu/bugs.c | 12 ++++++++++-- arch/x86/kernel/cpu/common.c | 6 +----- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 83f51cab0b1e..957e0df38d90 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -2181,7 +2181,14 @@ static void __init spectre_v2_select_mitigation(void) break; fallthrough; case SPECTRE_V2_CMD_FORCE: - if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { + /* + * Unless forced, don't use AutoIBRS when SNP is enabled + * because it degrades host userspace indirect branch performance. + */ + if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) && + (!boot_cpu_has(X86_FEATURE_SEV_SNP) || + (boot_cpu_has(X86_FEATURE_SEV_SNP) && + spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_FORCE))) { spectre_v2_enabled =3D SPECTRE_V2_EIBRS; break; } @@ -2261,7 +2268,8 @@ static void __init spectre_v2_apply_mitigation(void) =20 case SPECTRE_V2_IBRS: setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS); - if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) + if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) && + !boot_cpu_has(X86_FEATURE_SEV_SNP)) pr_warn(SPECTRE_V2_IBRS_PERF_MSG); break; =20 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index bb937bc4b00f..5aff1424a27d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1486,13 +1486,9 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x= 86 *c) /* * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature * flag and protect from vendor-specific bugs via the whitelist. - * - * Don't use AutoIBRS when SNP is enabled because it degrades host - * userspace indirect branch performance. */ if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || - (cpu_has(c, X86_FEATURE_AUTOIBRS) && - !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { + cpu_has(c, X86_FEATURE_AUTOIBRS)) { setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 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charset="utf-8" This is to prepare to allow legacy IBRS toggling on AMD systems, where the BTB Isolation SEV-SNP feature can use it to optimize the quick VM exit to re-entry path. There is no reason this wasn't allowed in the first place, therefore adding the cc: stable and Fixes: tags. Fixes: 7c693f54c873 ("x86/speculation: Add spectre_v2=3Dibrs option to supp= ort Kernel IBRS") Reported-by: Tom Lendacky Cc: Pawan Gupta Cc: Borislav Petkov (AMD) Cc: stable@kernel.org Signed-off-by: Kim Phillips --- v2: No changes v1: https://lore.kernel.org/kvm/20260224180157.725159-3-kim.phillips@amd.co= m/ arch/x86/kernel/cpu/bugs.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 957e0df38d90..c910da561044 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -2152,11 +2152,6 @@ static void __init spectre_v2_select_mitigation(void) spectre_v2_cmd =3D SPECTRE_V2_CMD_AUTO; } =20 - if (spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor= !=3D X86_VENDOR_INTEL) { - pr_err("IBRS selected but not Intel CPU. Switching to AUTO select\n"); - spectre_v2_cmd =3D SPECTRE_V2_CMD_AUTO; - } - if (spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATUR= E_IBRS)) { pr_err("IBRS selected but CPU doesn't have IBRS. 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charset="utf-8" This feature ensures SNP guest Branch Target Buffers (BTBs) are not affected by context outside that guest. CPU hardware tracks each guest's BTB entries and can flush the BTB if it has been determined to be contaminated with any prediction information originating outside the particular guest's context. To mitigate possible performance penalties incurred by these flushes, it is recommended that the hypervisor run with SPEC_CTRL[IBRS] set. Note that using Automatic IBRS is not an equivalent option here, since it behaves differently when SEV-SNP is active. See commit acaa4b5c4c85 ("x86/speculation: Do not enable Automatic IBRS if SEV-SNP is enabled") for more details. Indicate support for BTB Isolation in sev_supported_vmsa_features, bit 7. SNP-active guests can enable (BTB) Isolation through SEV_Status bit 9 (SNPBTBIsolation). For more info, refer to page 615, Section 15.36.17 "Side-Channel Protection", AMD64 Architecture Programmer's Manual Volume 2: System Programming Part 2, Pub. 24593 Rev. 3.42 - March 2024 (see Link). Link: https://bugzilla.kernel.org/attachment.cgi?id=3D306250 Signed-off-by: Kim Phillips --- v2: No changes v1: https://lore.kernel.org/kvm/20260224180157.725159-4-kim.phillips@amd.co= m/ arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/sev.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index edde36097ddc..2038461c1316 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -305,6 +305,7 @@ static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICA= L_MAX_INDEX_MASK) =3D=3D X2AV #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3) #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) +#define SVM_SEV_FEAT_BTB_ISOLATION BIT(7) #define SVM_SEV_FEAT_SECURE_TSC BIT(9) =20 #define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 3f9c1aa39a0a..ac29cf47dd08 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3167,6 +3167,9 @@ void __init sev_hardware_setup(void) =20 if (sev_snp_enabled && tsc_khz && cpu_feature_enabled(X86_FEATURE_SNP_SEC= URE_TSC)) sev_supported_vmsa_features |=3D SVM_SEV_FEAT_SECURE_TSC; + + if (sev_snp_enabled) + sev_supported_vmsa_features |=3D SVM_SEV_FEAT_BTB_ISOLATION; } =20 void sev_hardware_unsetup(void) --=20 2.43.0