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Wed, 11 Mar 2026 00:52:48 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:805b:14e9:f783:bcae]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35a0236f79asm727816a91.6.2026.03.11.00.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 00:52:47 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v5 3/7] PCI: mediatek-gen3: Move controller setup steps before PERST# control Date: Wed, 11 Mar 2026 15:52:18 +0800 Message-ID: <20260311075223.3303497-4-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog In-Reply-To: <20260311075223.3303497-1-wenst@chromium.org> References: <20260311075223.3303497-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting up the translation windows and enabling MSI involve only configuring the controller, not the device. These can be done before the device is enabled. Move these steps before the existing PERST# control. This provides a cleaner separation of controller vs device setup. This also allows the later patches that split out PERST# control and add device power control to have cleaner teardown. This change only moves code. No functional change is expected. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260309215056.GA603013@bhelgaas/ Signed-off-by: Chen-Yu Tsai --- Changes since v3: - New patch --- drivers/pci/controller/pcie-mediatek-gen3.c | 50 ++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 04ae195d36c2..1b6290f2c360 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -464,6 +464,31 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) val |=3D PCIE_DISABLE_DVFSRC_VLT_REQ; writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); =20 + mtk_pcie_enable_msi(pcie); + + /* Set PCIe translation windows */ + resource_list_for_each_entry(entry, &host->windows) { + struct resource *res =3D entry->res; + unsigned long type =3D resource_type(res); + resource_size_t cpu_addr; + resource_size_t pci_addr; + resource_size_t size; + + if (type =3D=3D IORESOURCE_IO) + cpu_addr =3D pci_pio_to_address(res->start); + else if (type =3D=3D IORESOURCE_MEM) + cpu_addr =3D res->start; + else + continue; + + pci_addr =3D res->start - entry->offset; + size =3D resource_size(res); + err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, + type, &table_index); + if (err) + return err; + } + /* * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal * causing occasional PCIe link down. In order to overcome the issue, @@ -510,31 +535,6 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) return err; } =20 - mtk_pcie_enable_msi(pcie); - - /* Set PCIe translation windows */ - resource_list_for_each_entry(entry, &host->windows) { - struct resource *res =3D entry->res; - unsigned long type =3D resource_type(res); - resource_size_t cpu_addr; - resource_size_t pci_addr; - resource_size_t size; - - if (type =3D=3D IORESOURCE_IO) - cpu_addr =3D pci_pio_to_address(res->start); - else if (type =3D=3D IORESOURCE_MEM) - cpu_addr =3D res->start; - else - continue; - - pci_addr =3D res->start - entry->offset; - size =3D resource_size(res); - err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, - type, &table_index); - if (err) - return err; - } - return 0; } =20 --=20 2.53.0.473.g4a7958ca14-goog