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Wed, 11 Mar 2026 00:52:41 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:805b:14e9:f783:bcae]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35a0236f79asm727816a91.6.2026.03.11.00.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 00:52:40 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 1/7] PCI: mediatek-gen3: Clean up mtk_pcie_parse_port() with dev_err_probe() Date: Wed, 11 Mar 2026 15:52:16 +0800 Message-ID: <20260311075223.3303497-2-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog In-Reply-To: <20260311075223.3303497-1-wenst@chromium.org> References: <20260311075223.3303497-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mtk_pcie_parse_port() in the pcie-mediatek-gen driver has a bunch of if (err) { dev_err(dev, "error message\n"); return err; # or goto } patterns. Simplify these with dev_err_probe(). The system also gains proper deferred probe messages that can be seen in /sys/kernel/debug/devices_deferred Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes in v5: - expanded tabs in commit message into spaces for better formatting in git log view (Bjorn) --- drivers/pci/controller/pcie-mediatek-gen3.c | 36 ++++++--------------- 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 75ddb8bee168..1939cac995b5 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -876,10 +876,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *p= cie) if (!regs) return -EINVAL; pcie->base =3D devm_ioremap_resource(dev, regs); - if (IS_ERR(pcie->base)) { - dev_err(dev, "failed to map register base\n"); - return PTR_ERR(pcie->base); - } + if (IS_ERR(pcie->base)) + return dev_err_probe(dev, PTR_ERR(pcie->base), "failed to map register b= ase\n"); =20 pcie->reg_base =3D regs->start; =20 @@ -888,34 +886,20 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *= pcie) =20 ret =3D devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets); - if (ret) { - dev_err(dev, "failed to get PHY bulk reset\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to get PHY bulk reset\n"); =20 pcie->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); - if (IS_ERR(pcie->mac_reset)) { - ret =3D PTR_ERR(pcie->mac_reset); - if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "failed to get MAC reset\n"); - - return ret; - } + if (IS_ERR(pcie->mac_reset)) + return dev_err_probe(dev, PTR_ERR(pcie->mac_reset), "failed to get MAC r= eset\n"); =20 pcie->phy =3D devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(pcie->phy)) { - ret =3D PTR_ERR(pcie->phy); - if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "failed to get PHY\n"); - - return ret; - } + if (IS_ERR(pcie->phy)) + return dev_err_probe(dev, PTR_ERR(pcie->phy), "failed to get PHY\n"); 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Wed, 11 Mar 2026 00:52:43 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v5 2/7] PCI: mediatek-gen3: Move mtk_pcie_setup_irq() out of mtk_pcie_setup() Date: Wed, 11 Mar 2026 15:52:17 +0800 Message-ID: <20260311075223.3303497-3-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog In-Reply-To: <20260311075223.3303497-1-wenst@chromium.org> References: <20260311075223.3303497-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mtk_pcie_setup_irq() just sets up the IRQ domains for PCI INTx and MSI, and chains them to the controller's interrupt. It's not really related to the setup of the actual PCIe controller. Move the mtk_pcie_setup_irq() call out of and before mtk_pcie_setup(), and add a proper error message for when it fails. Reorder mtk_pcie_irq_teardown() in the remove callback to follow. Also create an error path in the probe function. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260309215056.GA603013@bhelgaas/ Signed-off-by: Chen-Yu Tsai Reviewed-by: Bartosz Golaszewski --- Changes since v3: - New patch --- drivers/pci/controller/pcie-mediatek-gen3.c | 25 ++++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 1939cac995b5..04ae195d36c2 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1152,10 +1152,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) if (err) goto err_setup; =20 - err =3D mtk_pcie_setup_irq(pcie); - if (err) - goto err_setup; - return 0; =20 err_setup: @@ -1181,21 +1177,28 @@ static int mtk_pcie_probe(struct platform_device *p= dev) pcie->soc =3D device_get_match_data(dev); platform_set_drvdata(pdev, pcie); =20 + err =3D mtk_pcie_setup_irq(pcie); + if (err) + return dev_err_probe(dev, err, "Failed to setup IRQ domains\n"); + err =3D mtk_pcie_setup(pcie); if (err) - return err; + goto err_tear_down_irq; =20 host->ops =3D &mtk_pcie_ops; host->sysdata =3D pcie; =20 err =3D pci_host_probe(host); - if (err) { - mtk_pcie_irq_teardown(pcie); - mtk_pcie_power_down(pcie); - return err; - } + if (err) + goto err_power_down_pcie; =20 return 0; + +err_power_down_pcie: + mtk_pcie_power_down(pcie); +err_tear_down_irq: + mtk_pcie_irq_teardown(pcie); + return err; } =20 static void mtk_pcie_remove(struct platform_device *pdev) @@ -1208,8 +1211,8 @@ static void mtk_pcie_remove(struct platform_device *p= dev) pci_remove_root_bus(host->bus); pci_unlock_rescan_remove(); =20 - mtk_pcie_irq_teardown(pcie); mtk_pcie_power_down(pcie); + mtk_pcie_irq_teardown(pcie); } =20 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) --=20 2.53.0.473.g4a7958ca14-goog From nobody Thu Apr 9 04:05:07 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 411093B3BED for ; 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charset="utf-8" Setting up the translation windows and enabling MSI involve only configuring the controller, not the device. These can be done before the device is enabled. Move these steps before the existing PERST# control. This provides a cleaner separation of controller vs device setup. This also allows the later patches that split out PERST# control and add device power control to have cleaner teardown. This change only moves code. No functional change is expected. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260309215056.GA603013@bhelgaas/ Signed-off-by: Chen-Yu Tsai --- Changes since v3: - New patch --- drivers/pci/controller/pcie-mediatek-gen3.c | 50 ++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 04ae195d36c2..1b6290f2c360 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -464,6 +464,31 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) val |=3D PCIE_DISABLE_DVFSRC_VLT_REQ; writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); =20 + mtk_pcie_enable_msi(pcie); + + /* Set PCIe translation windows */ + resource_list_for_each_entry(entry, &host->windows) { + struct resource *res =3D entry->res; + unsigned long type =3D resource_type(res); + resource_size_t cpu_addr; + resource_size_t pci_addr; + resource_size_t size; + + if (type =3D=3D IORESOURCE_IO) + cpu_addr =3D pci_pio_to_address(res->start); + else if (type =3D=3D IORESOURCE_MEM) + cpu_addr =3D res->start; + else + continue; + + pci_addr =3D res->start - entry->offset; + size =3D resource_size(res); + err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, + type, &table_index); + if (err) + return err; + } + /* * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal * causing occasional PCIe link down. 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Wed, 11 Mar 2026 00:52:51 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:805b:14e9:f783:bcae]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35a0236f79asm727816a91.6.2026.03.11.00.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 00:52:50 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 4/7] PCI: mediatek-gen3: Add error path for resume driver callbacks Date: Wed, 11 Mar 2026 15:52:19 +0800 Message-ID: <20260311075223.3303497-5-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog In-Reply-To: <20260311075223.3303497-1-wenst@chromium.org> References: <20260311075223.3303497-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resume callback currently does teardown in the conditional block directly. This is going to get ugly when the pwrctrl calls are added. Move the teardown to a proper error cleanup path. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes since v3: - Dropped probe function error path; covered in previous patch --- drivers/pci/controller/pcie-mediatek-gen3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 1b6290f2c360..22a16e4ebc76 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1304,14 +1304,16 @@ static int mtk_pcie_resume_noirq(struct device *dev) return err; =20 err =3D mtk_pcie_startup_port(pcie); - if (err) { - mtk_pcie_power_down(pcie); - return err; - } + if (err) + goto err_power_down; =20 mtk_pcie_irq_restore(pcie); =20 return 0; + +err_power_down: + mtk_pcie_power_down(pcie); + return err; } =20 static const struct dev_pm_ops mtk_pcie_pm_ops =3D { --=20 2.53.0.473.g4a7958ca14-goog From nobody Thu Apr 9 04:05:07 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 948B73B4EA3 for ; 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charset="utf-8" In preparation for adding full power on/off control with the pwrctrl API, split out the existing code that only partially deals with device power sequencing into separate helper functions. The existing code only handles PERST#. This is purely moving code around, and brings no functional changes. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes since v4: - s/mtk_pcie_device_power_(up|down)/mtk_pcie_devices_power_(up|down)/ (Bjorn) Changes since v3: - Adapted to movement of existing setup code Changes since v1: - Updated commit message --- drivers/pci/controller/pcie-mediatek-gen3.c | 87 ++++++++++++--------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 22a16e4ebc76..526db8815401 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -403,6 +403,54 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *= pcie) writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); } =20 +static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie) +{ + int err; + u32 val; + + /* + * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal + * causing occasional PCIe link down. In order to overcome the issue, + * PCIE_RSTB signals are not asserted/released at this stage and the + * PCIe block is reset using en7523_reset_assert() and + * en7581_pci_enable(). + */ + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { + /* Assert all reset signals */ + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); + val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB; + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); + + /* De-assert reset signals */ + val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + return 0; +} + +static void mtk_pcie_devices_power_down(struct mtk_gen3_pcie *pcie) +{ + u32 val; + + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { + /* Assert the PERST# pin */ + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); + val |=3D PCIE_PE_RSTB; + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } +} + static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) { struct resource_entry *entry; @@ -489,33 +537,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) return err; } =20 - /* - * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal - * causing occasional PCIe link down. In order to overcome the issue, - * PCIE_RSTB signals are not asserted/released at this stage and the - * PCIe block is reset using en7523_reset_assert() and - * en7581_pci_enable(). - */ - if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { - /* Assert all reset signals */ - val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); - val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); - - /* De-assert reset signals */ - val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - } + err =3D mtk_pcie_devices_power_up(pcie); + if (err) + return err; =20 /* Check if the link is up or not */ err =3D readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, @@ -1270,7 +1294,6 @@ static int mtk_pcie_suspend_noirq(struct device *dev) { struct mtk_gen3_pcie *pcie =3D dev_get_drvdata(dev); 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charset="utf-8" If further setup fails after the device is powered on and link training succeeds, we want to place the device back in a quiescence state to avoid unintended activity and save power. This also helps with power state tracking and balancing once pwrctrl API is integrated. Power down the device in the error paths of mtk_pcie_startup_port() and mtk_pcie_probe(). Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes since v4: - Adapted to mtk_pcie_devices_power_down() name change Changes since v3: - Adapted to movement of existing setup code - Cleanup in mtk_pcie_setup() moved to mtk_pcie_probe() --- drivers/pci/controller/pcie-mediatek-gen3.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 526db8815401..208866d33c77 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -556,10 +556,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie= *pcie) dev_err(pcie->dev, "PCIe link down, current LTSSM state: %s (%#x)\n", ltssm_state, val); - return err; + goto err_power_down_device; } =20 return 0; + +err_power_down_device: + mtk_pcie_devices_power_down(pcie); + return err; } =20 #define MTK_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ @@ -1219,6 +1223,7 @@ static int mtk_pcie_probe(struct platform_device *pde= v) return 0; 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Wed, 11 Mar 2026 00:53:00 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 7/7] PCI: mediatek-gen3: Integrate new pwrctrl API Date: Wed, 11 Mar 2026 15:52:22 +0800 Message-ID: <20260311075223.3303497-8-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog In-Reply-To: <20260311075223.3303497-1-wenst@chromium.org> References: <20260311075223.3303497-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the new PCI pwrctrl API and PCI slot binding and power drivers, we now have a way to describe and power up WiFi/BT adapters connected through a PCIe or M.2 slot, or populated onto the mainboard itself. The latter case has the adapter layout or design copied verbatim, replacing the slot with direct connections. Integrate the PCI pwrctrl API into the PCIe driver, so that power is properly enabled before PCIe link training is done, allowing the card to successfully be detected. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes since v4: - Replaced "exploded" with "populated" and added explanation that the layout or design is copied verbatim (Bjorn) - Fix build break from label typo; fix was not squashed in correctly in my local tree Changes since v3: - Adapted changes to movement of existing setup code Changes since v2: - Added "select PCI_PWRCTRL_SLOT" to Kconfig to fix kernel test robot compilation error I'm wondering why the two existing uses select PCI_PWRCTRL_SLOT and not PCI_PWRCTRL though. --- drivers/pci/controller/Kconfig | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 38 ++++++++++++++++----- 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5aaed8ac6e44..e72ac6934379 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -222,6 +222,7 @@ config PCIE_MEDIATEK_GEN3 depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on PCI_MSI select IRQ_MSI_LIB + select PCI_PWRCTRL_SLOT help Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed, diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 208866d33c77..a94fdbaf47fe 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -421,15 +422,23 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_= pcie *pcie) val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + err =3D pci_pwrctrl_power_on_devices(pcie->dev); + if (err) { + dev_err(pcie->dev, "Failed to power on devices: %pe\n", ERR_PTR(err)); + return err; + } =20 - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); =20 + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { /* De-assert reset signals */ val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); @@ -449,6 +458,8 @@ static void mtk_pcie_devices_power_down(struct mtk_gen3= _pcie *pcie) val |=3D PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); } + + pci_pwrctrl_power_off_devices(pcie->dev); } =20 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) @@ -1209,9 +1220,15 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) return dev_err_probe(dev, err, "Failed to setup IRQ domains\n"); =20 + err =3D pci_pwrctrl_create_devices(pcie->dev); + if (err) { + goto err_tear_down_irq; + dev_err_probe(dev, err, "failed to create pwrctrl devices\n"); + } + err =3D mtk_pcie_setup(pcie); if (err) - goto err_tear_down_irq; + goto err_destroy_pwrctrl; =20 host->ops =3D &mtk_pcie_ops; host->sysdata =3D pcie; @@ -1225,6 +1242,9 @@ static int mtk_pcie_probe(struct platform_device *pde= v) err_power_down_pcie: mtk_pcie_devices_power_down(pcie); mtk_pcie_power_down(pcie); +err_destroy_pwrctrl: + if (err !=3D -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(pcie->dev); err_tear_down_irq: mtk_pcie_irq_teardown(pcie); return err; @@ -1240,7 +1260,9 @@ static void mtk_pcie_remove(struct platform_device *p= dev) pci_remove_root_bus(host->bus); pci_unlock_rescan_remove(); =20 + pci_pwrctrl_power_off_devices(pcie->dev); mtk_pcie_power_down(pcie); + pci_pwrctrl_destroy_devices(pcie->dev); mtk_pcie_irq_teardown(pcie); } =20 --=20 2.53.0.473.g4a7958ca14-goog