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charset="utf-8" Add device tree overlay to enable ICSSG0 dual EMAC support on AM642 EVM. This overlay enables both ICSSG0 Ethernet interfaces (port0 and port1) in dual EMAC mode. Users can combine this with the existing ICSSG1 overlay to enable all four ICSSG interfaces if needed. Signed-off-by: Meghana Malladi --- v3-v2 - Remove the aliases as they are not applicable for the overlay - Address all comments from Vignesh Raghavendra and ran D= T checks arch/arm64/boot/dts/ti/Makefile | 4 + .../boot/dts/ti/k3-am642-evm-icssg0.dtso | 168 ++++++++++++++++++ 2 files changed, 172 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index ba01a929e06f..d2cd124a5b08 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62x-sk-hdmi-audio.dtbo =20 # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-icssg0.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-icssg1-dualemac.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-icssg1-dualemac-mii.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-pcie0-ep.dtbo @@ -218,6 +219,8 @@ k3-am62p5-sk-csi2-ov5640-dtbs :=3D k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-ov5640.dtbo k3-am62p5-sk-csi2-tevi-ov5640-dtbs :=3D k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am642-evm-icssg0-dtbs :=3D \ + k3-am642-evm.dtb k3-am642-evm-icssg0.dtbo k3-am642-evm-icssg1-dualemac-dtbs :=3D \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-am642-evm-icssg1-dualemac-mii-dtbs :=3D \ @@ -306,6 +309,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-imx219.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ + k3-am642-evm-icssg0.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-evm-icssg1-dualemac-mii.dtb \ k3-am642-evm-pcie0-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso b/arch/arm64/b= oot/dts/ti/k3-am642-evm-icssg0.dtso new file mode 100644 index 000000000000..f19acf1896c3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM + * + * AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM + * DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE= -EVM + * + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + icssg0_eth: icssg0-eth { + compatible =3D "ti,am642-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pin= s_default>; + sram =3D <&oc_sram>; + + dmas =3D <&main_pktdma 0xc100 0>, /* egress slice 0 */ + <&main_pktdma 0xc101 0>, /* egress slice 0 */ + <&main_pktdma 0xc102 0>, /* egress slice 0 */ + <&main_pktdma 0xc103 0>, /* egress slice 0 */ + <&main_pktdma 0xc104 0>, /* egress slice 1 */ + <&main_pktdma 0xc105 0>, /* egress slice 1 */ + <&main_pktdma 0xc106 0>, /* egress slice 1 */ + <&main_pktdma 0xc107 0>, /* egress slice 1 */ + <&main_pktdma 0x4100 0>, /* ingress slice 0 */ + <&main_pktdma 0x4101 0>; /* ingress slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + interrupt-parent =3D <&icssg0_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + ti,prus =3D <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&= tx_pru0_1>; + firmware-name =3D "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg0_mii_g_rt>; + ti,mii-rt =3D <&icssg0_mii_rt>; + ti,iep =3D <&icssg0_iep0>, <&icssg0_iep1>; + ti,pa-stats =3D <&icssg0_pa_stats>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + icssg0_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg0_phy00>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&main_conf 0x4100>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + + icssg0_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg0_phy01>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&main_conf 0x4104>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + }; + }; +}; + +&main_pmx0 { + pru_icssg0_mdio_pins_default: pru-icssg0-mdio-pins { + pinctrl-single,pins =3D < + /* (P3) PRG0_MDIO0_MDC */ + AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) + /* (P2) PRG0_MDIO0_MDIO */ + AM64X_IOPAD(0x0200, PIN_INPUT, 0) + /* (P16) GPIO0_32 - GPMC0_ADVn_ALE - GPIO_ETH0/1_RESETn# */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) + >; + }; + + pru_icssg0_rgmii1_pins_default: pru-icssg0-rgmii1-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_R= D0 */ + AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_R= D1 */ + AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_R= D2 */ + AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_R= D3 */ + AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_R= XC */ + AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_= RX_CTL */ + AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_= TD0 */ + AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1= _TD1 */ + AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_= TD2 */ + AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_= TD3 */ + AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_= TXC */ + AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_= TX_CTL */ + >; + }; + + pru_icssg0_rgmii2_pins_default: pru-icssg0-rgmii2-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_R= D0 */ + AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_R= D1 */ + AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_R= D2 */ + AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_R= D3 */ + AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_R= XC */ + AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_R= X_CTL */ + AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_= TD0 */ + AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_= TD1 */ + AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_= TD2 */ + AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_= TD3 */ + AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2= _TXC */ + AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_= TX_CTL */ + >; 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charset="utf-8" Enable DP83TG720 PHY driver as a module to support TI's DP83TG720 1000BASE-T1 Automotive Ethernet PHY. This is required for the DP83TG720-IND-SPE-EVM daughter card used with AM642 EVM ICSSG0 interface. Signed-off-by: Meghana Malladi --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b67d5b1fc45b..3b88df2ca5e1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -420,6 +420,7 @@ CONFIG_REALTEK_PHY=3Dy CONFIG_ROCKCHIP_PHY=3Dy CONFIG_DP83867_PHY=3Dy CONFIG_DP83869_PHY=3Dm +CONFIG_DP83TG720_PHY=3Dm CONFIG_DP83TD510_PHY=3Dy CONFIG_VITESSE_PHY=3Dy CONFIG_XILINX_GMII2RGMII=3Dm --=20 2.43.0