From nobody Wed Apr 8 06:23:51 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B521036C592 for ; Wed, 11 Mar 2026 00:34:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773189248; cv=none; b=KrSvPlXuQFgle9Ht/qJQ+i1hrovIH2NN8kYI9vfjb1IhIFTJiA3T8kbZLadg5PqaitWPFn/0ocYH+yp7uNPAxYrwf7kJiQwNZMgvqUn4vQWL4vQDpW/kvkcWmul7PjsCxwfICdsph9PxpgmVh3Djx8CppcVKS0MXx8e5px0lPDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773189248; c=relaxed/simple; bh=W2LGyNZqQX/c9RYXmz11edzdl9owhvE9aNORh+BHn+A=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=iB+JY1hed0Dyiyh6Zy5FAHB1vTqWWqYZ/spQahNWQbyqek5TlBeigdYI1NCWZG8Yr1jg1hjMqObJ3IN7FFlnslPYio+fW5WvbEoHeRkKhpQy2KHdv1091s4u3I916lyo8MOgMIrNIqE7/+mWwHPDd+/VZkOq4I67ZmFnLN+lJ7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=wDTy0L/r; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wDTy0L/r" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-3598518beceso10316031a91.2 for ; Tue, 10 Mar 2026 17:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1773189245; x=1773794045; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=grOoDbAKPnsQ3mUYsQ7jw3YaC9t9ar7i6eOQ/Hn0Uzs=; b=wDTy0L/r9563amgzh5j81Q6qoSiD4Oy602eLFgsnGW4IfkTpMkpFy3IPKzLLs9oWu8 elEgsC4HXSM4bC2UeywZwwMbP46GvZEfgfL3BZ9MsMv45ZDOZTXg1IUba058vJ7gXv5r qUBmToe+kFDjSxeJV+yrijvljRxQjYXroeEOItSSf8sdhROmm3rm2joK0RcfpnOoPcwk 6igIDUl8U0JlUC+OuXVtjhLikKKRbmPnmBQp4mtl/xrNTNmsDpBwgT2PQmIugVQ6Ao4l nKgVYcOGX+i6csOYUDZn7IusQ4XqHMyT+WasEEmlFRhO02CyVPaJaIjxaWIsLo4UREs+ WkoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773189245; x=1773794045; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=grOoDbAKPnsQ3mUYsQ7jw3YaC9t9ar7i6eOQ/Hn0Uzs=; b=qP2pJ0S55uOYbwJ6kU2+bXzAy/000ucdvLqI1OjFka7vkCmVgQov41hS3f4IYsoqr5 SCVDTlTowqqvMo0iebG/pGSW59eMIQgXYJZSie2FIpCtuppmKRKaW/jdK2hphdjxXwmu ryFGoCHMZqpxFuFjx71y7wm/O7X1vnBjOcVPbT2QtqQJJjY6bbgw9DmKGv+d1KMLqiUI aVeRMcKsV8WskNg6fyG4oKEDx1ja5eCfFF1is0A0XEYk0bSbcubdgB84pKOkmaQPcUkA M8IssgP/nnbfLKo9iD4oMsarmx32+C27rJ3L+AMC649CVQwWqxTDW1Qov71utyIYXSvp 3RoQ== X-Forwarded-Encrypted: i=1; AJvYcCXIQxykMH+OVfti15iLuZdVUh5081l7KcApSWozt+V4kHx3M+a6Kj9EZSI+ZWAbH6yKhj3yZ2uus6L42tY=@vger.kernel.org X-Gm-Message-State: AOJu0Yxg1vuja6SyjoE9abau0ZPDGUgMgh/15wVni7wqpLxCq/6BgQ+R P+RnCkZ90aOSBTW3d8zaYYQHkLcqypYbVpuZxjFpq8LkwfJo6UGag5mNN74ZtoHr88CSrSCU302 nifS/Nw== X-Received: from pjam23.prod.google.com ([2002:a17:90a:1597:b0:359:9051:f779]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1642:b0:359:94d8:34e7 with SMTP id 98e67ed59e1d1-35a01367b6amr697319a91.32.1773189245076; Tue, 10 Mar 2026 17:34:05 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 10 Mar 2026 17:33:45 -0700 In-Reply-To: <20260311003346.2626238-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260311003346.2626238-1-seanjc@google.com> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog Message-ID: <20260311003346.2626238-7-seanjc@google.com> Subject: [PATCH 6/7] KVM: x86: Use a proper bitmap for tracking available/dirty registers From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Kiryl Shutsemau Cc: kvm@vger.kernel.org, x86@kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Chang S . Bae" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define regs_{avail,dirty} as bitmaps instead of U32s to harden against overflow, and to allow for dynamically sizing the bitmaps when APX comes along, which will add 16 more GPRs (R16-R31) and thus increase the total number of registers beyond 32. Open code writes in the "reset" APIs, as the writes are hot paths and bitmap_write() is complete overkill for what KVM needs. Even better, hardcoding writes to entry '0' in the array is a perfect excuse to assert that the array contains exactly one entry, e.g. to effectively add guard against defining R16-R31 in 32-bit kernels. For all intents and purposes, no functional change intended even though using bitmap_fill() will mean "undefined" registers are no longer marked available and dirty (KVM should never be querying those bits). Signed-off-by: Sean Christopherson --- arch/x86/include/asm/kvm_host.h | 6 ++++-- arch/x86/kvm/kvm_cache_regs.h | 21 +++++++++++++-------- arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 734c2eee58e0..cff9023f12c7 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -211,6 +211,8 @@ enum kvm_reg { VCPU_REG_SEGMENTS, VCPU_REG_EXIT_INFO_1, VCPU_REG_EXIT_INFO_2, + + NR_VCPU_TOTAL_REGS, }; =20 enum { @@ -802,8 +804,8 @@ struct kvm_vcpu_arch { */ unsigned long regs[NR_VCPU_GENERAL_PURPOSE_REGS]; unsigned long rip; - unsigned long regs_avail; - unsigned long regs_dirty; + DECLARE_BITMAP(regs_avail, NR_VCPU_TOTAL_REGS); + DECLARE_BITMAP(regs_dirty, NR_VCPU_TOTAL_REGS); =20 unsigned long cr0; unsigned long cr0_guest_owned_bits; diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 5de6c7dfd63b..782710829608 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -67,29 +67,29 @@ static inline bool kvm_register_is_available(struct kvm= _vcpu *vcpu, enum kvm_reg reg) { kvm_assert_register_caching_allowed(vcpu); - return test_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); + return test_bit(reg, vcpu->arch.regs_avail); } =20 static inline bool kvm_register_is_dirty(struct kvm_vcpu *vcpu, enum kvm_reg reg) { kvm_assert_register_caching_allowed(vcpu); - return test_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty); + return test_bit(reg, vcpu->arch.regs_dirty); } =20 static inline void kvm_register_mark_available(struct kvm_vcpu *vcpu, enum kvm_reg reg) { kvm_assert_register_caching_allowed(vcpu); - __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); + __set_bit(reg, vcpu->arch.regs_avail); } =20 static inline void kvm_register_mark_dirty(struct kvm_vcpu *vcpu, enum kvm_reg reg) { kvm_assert_register_caching_allowed(vcpu); - __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); - __set_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty); + __set_bit(reg, vcpu->arch.regs_avail); + __set_bit(reg, vcpu->arch.regs_dirty); } =20 /* @@ -102,12 +102,15 @@ static __always_inline bool kvm_register_test_and_mar= k_available(struct kvm_vcpu enum kvm_reg reg) { kvm_assert_register_caching_allowed(vcpu); - return arch___test_and_set_bit(reg, (unsigned long *)&vcpu->arch.regs_ava= il); + return arch___test_and_set_bit(reg, vcpu->arch.regs_avail); } =20 static __always_inline void kvm_reset_available_registers(struct kvm_vcpu = *vcpu, unsigned long available_mask) { + BUILD_BUG_ON(sizeof(available_mask) !=3D sizeof(vcpu->arch.regs_avail[0])= ); + BUILD_BUG_ON(ARRAY_SIZE(vcpu->arch.regs_avail) !=3D 1); + /* * Note the bitwise-AND! In practice, a straight write would also work * as KVM initializes the mask to all ones and never clears registers @@ -115,13 +118,15 @@ static __always_inline void kvm_reset_available_regis= ters(struct kvm_vcpu *vcpu, * sanity checking as incorrectly marking an eagerly sync'd register * unavailable will generate a WARN due to an unexpected cache request. */ - vcpu->arch.regs_avail &=3D available_mask; + vcpu->arch.regs_avail[0] &=3D available_mask; } =20 static __always_inline void kvm_reset_dirty_registers(struct kvm_vcpu *vcp= u, unsigned long dirty_mask) { - vcpu->arch.regs_dirty =3D dirty_mask; + BUILD_BUG_ON(sizeof(dirty_mask) !=3D sizeof(vcpu->arch.regs_dirty[0])); + BUILD_BUG_ON(ARRAY_SIZE(vcpu->arch.regs_dirty) !=3D 1); + vcpu->arch.regs_dirty[0] =3D dirty_mask; } =20 /* diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index dd39ccbff0d6..c1e1b3030786 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -12809,8 +12809,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) int r; =20 vcpu->arch.last_vmentry_cpu =3D -1; - vcpu->arch.regs_avail =3D ~0; - vcpu->arch.regs_dirty =3D ~0; + bitmap_fill(vcpu->arch.regs_avail, NR_VCPU_TOTAL_REGS); + bitmap_fill(vcpu->arch.regs_dirty, NR_VCPU_TOTAL_REGS); =20 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm); =20 --=20 2.53.0.473.g4a7958ca14-goog