From nobody Wed Apr 8 06:23:51 2026 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B712F366077 for ; Wed, 11 Mar 2026 00:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773189244; cv=none; b=dP6D+AjSvkiURCWPqQQWDX8hwRLQEpPxij5PEKhqAoejmCokwtaVhX9DYT1ijlsneDVQlwkESEQJqi7aL08O4Pb82MuqgQrtbvwQhM2ZmDs3dM2D5ERlgkSVMHfN4bSgqNJmga0Apoj3ikUPnpz4dbsV2aHlZav3QlKsNJm5P4g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773189244; c=relaxed/simple; bh=/AZ+SwQNuV1HBEW+2zllqRNISfAa3nxcBibWN/35fOM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=T0uaL/lwCwN9mrleCPXcW1o6eCtDhZUgPXjqVv650pylIDMZtmGt+a2UQR1x7BzYC71kNZZGRJJN3PMMmeMRtt34olomDbKGmeFL4yJ9I/uerJSi7KBUNRk8xzjhkGMg2/2L8v0sINlJ1qxx292PzQae7AcT7t0wEfPv/TpgxWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=T1ahHzBV; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="T1ahHzBV" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-8298c733f52so187920b3a.0 for ; Tue, 10 Mar 2026 17:34:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1773189241; x=1773794041; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=VrwT1qYZM1BVcF4TouPNh26klS1cOdhqo+z3t1px/qc=; b=T1ahHzBVDJ2gVUp2qFuRNU6/Mo1l0ksXq40Z7X4T9QleJXu1/EmfPPcZ/S5Kl0Q7le vqiixRzXbIEIx/1lmHc+lZcNJluj5oiFiZu5RbA+13Ppfcvt/5039Bbkcn9OBdTqXc6/ fsICG3iEQ0E83yNFVaEt0P2nIjsP2lmYrPVQyStj/PzsuxMZ2x4r5/Kf26APXk3slj3z gAj5AkRVhueSjWJHQzGPMoC132Kd9qVCKS20cvpCXsVWjFh/PJ+Q/fWVcjJFURCNKuBC 4y/2IB7VpOGvLc0v4unnkGdwjTWCB29yDd8RVoA3a4Yibveky0AaNIcA6avVjZSPAq1+ z+aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773189241; x=1773794041; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VrwT1qYZM1BVcF4TouPNh26klS1cOdhqo+z3t1px/qc=; b=GOkY2ut/yd9uMLNN8/june6KDA5U8IwRpoSYznhYHDJtZZWYgj3wBTkFq8ga+A/Mrr kR5eP6hAr/iDgW1H52AWpHzE3LLkbQUG5dog0EUhOjvBhJvyr2NwnO4/AjIyC/r0Bs9i OWiLxWtpF7mJoESD+E7mapN/rVvX0/sgv380HrJi00fr0MMvFHcbuTaYIWkf5U9XzmV8 Uwn3b8PPc4w17ZLfMB+1MwdoUC6/glw4sn/szZUrwDuDezwtztud9C0Bt+2X2cp9pQoW aB4E7xFXfN8bz9BSMJYp+ACGuJ+DGxAPL8i+jW5BG23fHZvvX7lAAHUIWbAJyhNyQNCC mbqw== X-Forwarded-Encrypted: i=1; AJvYcCWaGTafMQTd+qjPnwjZNI66/wIR+au99lbqeINM0kfCkMpPJPi8ZjkkqE8pEAL0N9bQE7ExbQBd8cEye5E=@vger.kernel.org X-Gm-Message-State: AOJu0YwDQybH9njDNnZpDXL0egmN6CglRh+NAae1hx928mjGPFz+WvD4 UPHcIKkrcuzcPaTe3AEbYy8DIDH0o5NbXiuDtHJN+pOJRFKHRy7bBmtQHTyqiTSrFD9ckhnDEif 0WV1Zkw== X-Received: from pfbfm23.prod.google.com ([2002:a05:6a00:2f97:b0:823:747:7567]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:21d1:b0:825:2927:3aa6 with SMTP id d2e1a72fcca58-829f79d5943mr495224b3a.14.1773189240997; Tue, 10 Mar 2026 17:34:00 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 10 Mar 2026 17:33:43 -0700 In-Reply-To: <20260311003346.2626238-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260311003346.2626238-1-seanjc@google.com> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog Message-ID: <20260311003346.2626238-5-seanjc@google.com> Subject: [PATCH 4/7] KVM: x86: Add wrapper APIs to reset dirty/available register masks From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Kiryl Shutsemau Cc: kvm@vger.kernel.org, x86@kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Chang S . Bae" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add wrappers for setting regs_{avail,dirty} in anticipation of turning the fields into proper bitmaps, at which point direct writes won't work so well. Deliberately leave the initialization in kvm_arch_vcpu_create() as-is, because the regs_avail logic in particular is special in that it's the one and only place where KVM marks eagerly synchronized registers as available. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/kvm_cache_regs.h | 19 +++++++++++++++++++ arch/x86/kvm/svm/svm.c | 4 ++-- arch/x86/kvm/vmx/nested.c | 4 ++-- arch/x86/kvm/vmx/tdx.c | 2 +- arch/x86/kvm/vmx/vmx.c | 4 ++-- 5 files changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index ac1f9867a234..94e31cf38cb8 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -105,6 +105,25 @@ static __always_inline bool kvm_register_test_and_mark= _available(struct kvm_vcpu return arch___test_and_set_bit(reg, (unsigned long *)&vcpu->arch.regs_ava= il); } =20 +static __always_inline void kvm_reset_available_registers(struct kvm_vcpu = *vcpu, + u32 available_mask) +{ + /* + * Note the bitwise-AND! In practice, a straight write would also work + * as KVM initializes the mask to all ones and never clears registers + * that are eagerly synchronized. Using a bitwise-AND adds a bit of + * sanity checking as incorrectly marking an eagerly sync'd register + * unavailable will generate a WARN due to an unexpected cache request. + */ + vcpu->arch.regs_avail &=3D available_mask; +} + +static __always_inline void kvm_reset_dirty_registers(struct kvm_vcpu *vcp= u, + u32 dirty_mask) +{ + vcpu->arch.regs_dirty =3D dirty_mask; +} + /* * The "raw" register helpers are only for cases where the full 64 bits of= a * register are read/written irrespective of current vCPU mode. In other = words, diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 1712c21f4128..1a6626c32188 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4524,7 +4524,7 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_= vcpu *vcpu, u64 run_flags) vcpu->arch.regs[VCPU_REGS_RSP] =3D svm->vmcb->save.rsp; vcpu->arch.rip =3D svm->vmcb->save.rip; } - vcpu->arch.regs_dirty =3D 0; + kvm_reset_dirty_registers(vcpu, 0); =20 if (unlikely(svm->vmcb->control.exit_code =3D=3D SVM_EXIT_NMI)) kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); @@ -4570,7 +4570,7 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_= vcpu *vcpu, u64 run_flags) vcpu->arch.apf.host_apf_flags =3D kvm_read_and_reset_apf_flags(); =20 - vcpu->arch.regs_avail &=3D ~SVM_REGS_LAZY_LOAD_SET; + kvm_reset_available_registers(vcpu, ~SVM_REGS_LAZY_LOAD_SET); =20 if (!msr_write_intercepted(vcpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL)) rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, vcpu_to_pmu(vcpu)->global_ctrl); diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index af2aaef38502..d4ba64bde709 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -310,13 +310,13 @@ static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, st= ruct loaded_vmcs *vmcs) vmx_sync_vmcs_host_state(vmx, prev); put_cpu(); =20 - vcpu->arch.regs_avail &=3D ~VMX_REGS_LAZY_LOAD_SET; + kvm_reset_available_registers(vcpu, ~VMX_REGS_LAZY_LOAD_SET); =20 /* * All lazily updated registers will be reloaded from VMCS12 on both * vmentry and vmexit. */ - vcpu->arch.regs_dirty =3D 0; + kvm_reset_dirty_registers(vcpu, 0); } =20 static void nested_put_vmcs12_pages(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index c23ec4ac8bc8..d4cb6dc8098f 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -1098,7 +1098,7 @@ fastpath_t tdx_vcpu_run(struct kvm_vcpu *vcpu, u64 ru= n_flags) =20 tdx_load_host_xsave_state(vcpu); =20 - vcpu->arch.regs_avail &=3D TDX_REGS_AVAIL_SET; + kvm_reset_available_registers(vcpu, TDX_REGS_AVAIL_SET); =20 if (unlikely(tdx->vp_enter_ret =3D=3D EXIT_REASON_EPT_MISCONFIG)) return EXIT_FASTPATH_NONE; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ed44eb5b4349..217ea6e72c2f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7472,7 +7472,7 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vc= pu *vcpu, flags); =20 vcpu->arch.cr2 =3D native_read_cr2(); - vcpu->arch.regs_avail &=3D ~VMX_REGS_LAZY_LOAD_SET; + kvm_reset_available_registers(vcpu, ~VMX_REGS_LAZY_LOAD_SET); =20 vmx->idt_vectoring_info =3D 0; =20 @@ -7538,7 +7538,7 @@ fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu, u64 ru= n_flags) vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); if (kvm_register_is_dirty(vcpu, VCPU_REG_RIP)) vmcs_writel(GUEST_RIP, vcpu->arch.rip); - vcpu->arch.regs_dirty =3D 0; + kvm_reset_dirty_registers(vcpu, 0); =20 if (run_flags & KVM_RUN_LOAD_GUEST_DR6) set_debugreg(vcpu->arch.dr6, 6); --=20 2.53.0.473.g4a7958ca14-goog