From nobody Wed Apr 8 02:51:49 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A020F36EA9D for ; Wed, 11 Mar 2026 03:24:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773199464; cv=none; b=Py2NWXoqVJdGMtoyp+Ysn4FSA9cpSboV5344KoE9pcUB2qSdnbRQ1dSQ0oW3q1zRFacSmX3uMTp+F/WMa+W4QnNQSzYrDywpyOmVUaHg0C8yr+BttlEabFjqOPXVW09F1eGHxpmCLsVmeV6uriTT2mpM6lAqGN2txsbtBH2wudw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773199464; c=relaxed/simple; bh=Q5MIUHiSxbGVEdUF7Mbz0DMJwk2qxjWolhKQbh9xwlg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BVS4jq1QSIMhTGwawzayGGfnkIDxSj+/+tNvLqYoi0obiZpc00meagwzPhTfppb/2QRJ5uwXOgrBkG8Lll5DGm41pY6tACLI9iqTyBbo5vCBfNkjusQWCF4W68YR7kkQG5Uu2UkezFj7BbG4mHI5gA+F8lYknFcMfKprTVlz5rU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ntjZcPHD; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=FWjMhjzA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ntjZcPHD"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="FWjMhjzA" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62B17M1s508294 for ; Wed, 11 Mar 2026 03:24:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +xGen/0FzexLqmKExWBIL2m3ElpzS8KM21Ro0B4OQGs=; b=ntjZcPHDBjyiH+Ti 3uT19/VXp70spwnBT/rNi8s6cvm2nhF0TSxH2KAr+gklhZN3gE4umhP/9HR7ZGpL kf7JqN9yyx4KfkXpBxIYKJ4UidiOEyeyPwg/I/ySANzp6uxlyApuTXB/SDJlRSs0 g1Mj+jzwUAsgQ2qN/ia8er70JDuFPuZbNikEPmy/9oVhyb+maBgEly8aQt+JZiyH 1kNroUnXpXNeO2iEZp8hrorHWLv9/5X5al5K00DFtRzZm1qmsZ8oQUeWwojfW9KG giqL8xchnC9Ca3auh9iEXM2JheDnXHO32L5QrROntl/n+qPjwojU1bFwI7WixFet XICqXg== Received: from mail-vs1-f71.google.com (mail-vs1-f71.google.com [209.85.217.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ctppaj141-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 03:24:18 +0000 (GMT) Received: by mail-vs1-f71.google.com with SMTP id ada2fe7eead31-5ffaf5b522eso41215680137.1 for ; Tue, 10 Mar 2026 20:24:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773199458; x=1773804258; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+xGen/0FzexLqmKExWBIL2m3ElpzS8KM21Ro0B4OQGs=; b=FWjMhjzAXshuHg6MUO6lp/YDwGwuSLaeXQ8Nc70aGP53BzZAEGA8MpoR8ciawwXaMV NVD0hkFnX1A2gcBUy6GGLl1ZyWXizn28ElzgQt6ZrlPAV+H4nYDtR7QuryobzxHDJk+S UHjrE4baxnEb1OqofgJRlRnr7gIiasM1eYTGrxCukZBmoS9PPcA1frR8gi5X6nidnR3f Q+Drkg1cFXIysEFh59D8KaZLnnPOMjnZcF2OPDLAJQmLmYOw73ch5gqLRw6CnGliPl/w NbXQ0k2FtS3UjTDM6IwPo+I4C9HiQyhjHstH9lMijtdz87FXXjozYeJIsZzwkktOeFZs ZvpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773199458; x=1773804258; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+xGen/0FzexLqmKExWBIL2m3ElpzS8KM21Ro0B4OQGs=; b=TZbqg2vux+vl6YbOWpyXwocY5tlnJWW3DRwlhddzNalxCvjvAb/neMUUMV1bOM7CiN HQDKHGZOFM/jsMUsnzvE7q85xJDnlcC3O5IpAWZkoFHRzEovwqVBNcn63s2zbNU+j3MC mq7qTPoHZsW55p1e+LYhobpxte1DJNzDXi93fGM2H/mfpaOn1V7j8k5LzIGcvb4jOHZ5 XsHADTVteyh5Au8F4/6uzAtWSXKu31aQA73nPnPMWed42VFoMliUGGRxlvteK/nCglJ4 kd/EuhGz5NqoW7Z9AhdPZ6sceX1tfNpkmDQVgkL2cInwCRGdMU4XstQs2Npn9AQSl6O9 bkoQ== X-Forwarded-Encrypted: i=1; AJvYcCV1UQY+buyFPWqsC6m+S2S4l8GYgkfiwXH+PKZmBEO/zmIi54shTLNeUFI9UyyXfwXKT2xIn2uSizhpFxk=@vger.kernel.org X-Gm-Message-State: AOJu0Yxhcd0n4k40w0X2fALjpLzJSV5Sv+KioDNutAapyR9p9FIJAWBo OUxgr+rMyPrdpiaAgk8jluBs2TcKbk2n697/MU2XmYww4Y53uFdwxhkMbBNT+15bUxAtH8yLm/g hZnJl2iSvFi3sd54lZTwaGco698ZraLI+/djrTQjVYx9CL3a6qaAEfORWPHRyvibs4vE= X-Gm-Gg: ATEYQzw+bCbt72r8+lhr4hJb1dfe6B7OwPErlVvL2zg4vFdaC5HOKWh7EEi/9aFGIM2 3R7Hc5u7suiYeVEyMJYmL+xKWc0xtWB/MqzTcb63uBraL8UkhmYRkhIMv2m3N05gTjZpoRNWRQM Tz9O6q9kpCtXAzhq2DHwy+qBNSuEhjgT+RqrBAf++unw4t7+MiUwjhSFWLJUWaIrgSwbqiFK8ju gE88UDdB5yRszPO7nNSdhQn/8kwfT/UUzYDziNiSOjvp1lB8fYxsE1fzNVCqIBFsPv88UOg8yim 2DzgX5ZqOCX6kDZSP+wzCPDbs+FPz/0JCQch0UtAxvXtVdUEpyO+doeiL+V/rGqYqvWx/y9uyib vG02DLIZe56D1e/LYaJlCmcihnqprQ84QB0FqOR5DzGhVnJMS1hM1pKiQdQ8voGjgd+nfIO87sz qydi4iRbnURtKk6YpaPEBobhilXWZpIeZ+kuA= X-Received: by 2002:a05:6102:512b:b0:5db:ca9e:b57d with SMTP id ada2fe7eead31-601def4f45emr498319137.19.1773199457543; Tue, 10 Mar 2026 20:24:17 -0700 (PDT) X-Received: by 2002:a05:6102:512b:b0:5db:ca9e:b57d with SMTP id ada2fe7eead31-601def4f45emr498300137.19.1773199457034; Tue, 10 Mar 2026 20:24:17 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ed41sm1422721fa.25.2026.03.10.20.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 20:24:14 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 11 Mar 2026 05:23:17 +0200 Subject: [PATCH v2 23/25] soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ubwc-rework-v2-23-69f718f2a1c9@oss.qualcomm.com> References: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> In-Reply-To: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5999; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Q5MIUHiSxbGVEdUF7Mbz0DMJwk2qxjWolhKQbh9xwlg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsOAgU3yCGHPGEzdrmenVuVhAY4o838XvB+HzL 8v84IHDn+yJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabDgIAAKCRCLPIo+Aiko 1bKrCACbiQPWPt6lqeYVgOqnd3/PZglPIeRLdzx6AB0vn0PZnSQw9mMeNqMYWLZzy0Nm1egQExu 938S5fN4Ex8OGTAOrpsCDTIkbvGGK0atWpug5K9y2m1o0AczY1a9z/FEogI4eGaDFxn1UgIbL3Q AYm3U4+DNRdSo3KhZ91rqQZIJf0ZmLbZDP1ywAbhBljaB54xVOwj6JXLMOX3qPwZg8lqfAUsjaR 7vh1Rh/hTQB22D6qtjbCRba9XrGwhEI7oiNnzCDTqnJoxyOTjH7MSHb7yVDnS4DvMo5NZ/wZK4X PeJP95+X/0cEJnoEGURHFmyaXrBHS6iSzFt0AQH2VnY8fPQD X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: UBBjERVcmgxzul1JhLWR9w5L8_T9UVmt X-Authority-Analysis: v=2.4 cv=D7BK6/Rj c=1 sm=1 tr=0 ts=69b0e062 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=8a_ODPMxA7UucN5sxwIA:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDAyNiBTYWx0ZWRfX8UqM9tMRVxnm +j5ELI+BKYkEDib+nhBX61oDoGETMSETYJ/yG4ozulrKmp5wMsMrvJGD1tBaUbvIvqF07C3J5yu +IZotC4d2G8zdUhs/uJZTncfCVWyR89+xrLtJPu90SGH+A0Ju0jpXiaMBN3+OOk1/lSjG7YX3jN ySDXnmknllGiP/ui+kjrzzGWyg+HNHjvxLVNLj2FQwF97BqdJZ15CPfn3JXNEa9WdOIgl1g8Frf G5S+z0u/PfqC9QLYMZvNpCf2p0XssFVFDUX4OExApIh5ZCtNui/ehYj3x6nFeh2TAM+kKgVe2cr WTip3tLR/eArYhs7ID7qtTYUfDQ0RU/0unaadqm3TFzNjFut13cIadnFTl7KJdM9zNZqbTC3F5f /PfznQP2LLFIvYh2DY/hkTdRO9RWSj4H7ZzSUa12aVbuBhWMqBX8mZXV4Vs3QwOtK3JwURd4eIf jQLZt7fu1+5fa+cWl9g== X-Proofpoint-ORIG-GUID: UBBjERVcmgxzul1JhLWR9w5L8_T9UVmt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_05,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110026 UBWC devices before 4.0 use standard UBWC swizzle levels. As all the drivers now use the qcom_ubwc_swizzle() helper, move those values to the helper, leaving UBWC 4.0+ intact for now. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 34 ---------------------------------- include/linux/soc/qcom/ubwc.h | 33 ++++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 43 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 51de36f5f40b..49edfabb5e18 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -25,17 +25,11 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = =3D { =20 static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 @@ -52,94 +46,66 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D= { =20 static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_1, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 13, }; =20 static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_1, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, }; =20 static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, }; =20 static const struct qcom_ubwc_cfg_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index d4a0cfb133fa..0cbd20078ada 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -22,9 +22,6 @@ struct qcom_ubwc_cfg_data { * UBWC 4.0 adds the optional ability to disable levels 2 & 3. */ u32 ubwc_swizzle; -#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) -#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) -#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) =20 /** * @highest_bank_bit: Highest Bank Bit @@ -55,12 +52,7 @@ static inline const struct qcom_ubwc_cfg_data *qcom_ubwc= _config_get_data(void) =20 static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data= *cfg) { - bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; - - if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) - pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); - - return ret; + return cfg->ubwc_enc_version =3D=3D UBWC_1_0; } =20 /* @@ -88,8 +80,31 @@ static inline bool qcom_ubwc_bank_spread(const struct qc= om_ubwc_cfg_data *cfg) return true; } =20 +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) + +/** + * @qcom_ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. + * + * UBWC 1.0 always enables all three levels. + * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. + * UBWC 4.0 adds the optional ability to disable levels 2 & 3. + */ static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) { + if (cfg->ubwc_enc_version =3D=3D 0) + return 0; + + if (cfg->ubwc_enc_version =3D=3D UBWC_1_0) + return UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3; + + if (cfg->ubwc_enc_version < UBWC_4_0) + return UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3; + return cfg->ubwc_swizzle; } =20 --=20 2.47.3