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It's just not all targets have separate bit to control it. Drop the bit from the database and make the helper always return true. If we need to change it later, the helper can be adjusted according to the programming guides. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 13 ------------- include/linux/soc/qcom/ubwc.h | 3 +-- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index c5c7fcb4d013..070bf97e134e 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -20,7 +20,6 @@ static const struct qcom_ubwc_cfg_data kaanapali_data =3D= { .ubwc_enc_version =3D UBWC_6_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 16, .macrotile_mode =3D true, }; @@ -49,7 +48,6 @@ static const struct qcom_ubwc_cfg_data qcm2290_data =3D { static const struct qcom_ubwc_cfg_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, }; @@ -58,7 +56,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, }; @@ -67,7 +64,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; =20 @@ -75,7 +71,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, .macrotile_mode =3D true, }; @@ -92,7 +87,6 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 16, .macrotile_mode =3D true, }; @@ -116,7 +110,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; =20 @@ -139,7 +132,6 @@ static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; =20 @@ -161,7 +153,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -171,7 +162,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -181,7 +171,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -190,7 +179,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data =3D { static const struct qcom_ubwc_cfg_data sm8750_data =3D { .ubwc_enc_version =3D UBWC_5_0, .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -199,7 +187,6 @@ static const struct qcom_ubwc_cfg_data sm8750_data =3D { static const struct qcom_ubwc_cfg_data glymur_data =3D { .ubwc_enc_version =3D UBWC_5_0, .ubwc_swizzle =3D 0, - .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, .macrotile_mode =3D true, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index c5f049eab07d..405d83f8d95b 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -33,7 +33,6 @@ struct qcom_ubwc_cfg_data { * DDR bank. This should ideally use DRAM type detection. */ int highest_bank_bit; - bool ubwc_bank_spread; =20 /** * @macrotile_mode: Macrotile Mode @@ -88,7 +87,7 @@ static inline bool qcom_ubwc_macrotile_mode(const struct = qcom_ubwc_cfg_data *cfg =20 static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *= cfg) { - return cfg->ubwc_bank_spread; + return true; } =20 static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) --=20 2.47.3