From nobody Tue Apr 7 02:35:52 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1788A3B47C0 for ; Wed, 11 Mar 2026 07:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215348; cv=none; b=kxxcIpUa2le13BD2KfoMg5KfAh820LBYTp4HuFej3ztoyyjP/Y8dBEeCiPlyOUMh6V/V4xIwYCyV4Jq/08DSYWwT9njpBVjekRJuRWdD9kvL0cMsGEpQfxlLgUEOlRavDAFY95QHKK4Ln2bl2UboBZr+SEjBkqMIB15nhiPuToo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215348; c=relaxed/simple; bh=fGbnE6hMtBI7kYckW9H/SvVRjm5yFP4M95RhcvAmLzQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r2KCiYfbejilRX8xQIUaMBWhPKHgQK3PVj1BWGoNtq91HIkkB1tD/DrRUR1oId1nzEk7d1hfHFY6QuFZud+AZXc2IGNro2x2tA/zC5ZvdvSVku/EilZudQlb/IVH55DIAS/LVodMkHE8JQkzUFuRUrqW35q80rC8mK+OgrqZFgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=M42LA7ht; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="M42LA7ht" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 895D412D6; Wed, 11 Mar 2026 08:47:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1773215256; bh=fGbnE6hMtBI7kYckW9H/SvVRjm5yFP4M95RhcvAmLzQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=M42LA7htyXp83Ccx5faAX/Ap+keIorOcKAAQvOqSL/+Q3kAHs3OpfVMnVOX2gJUvf aTkfyRSp/4xxcfnuKYx9+ADgmMApiEmuxgWYyCBC42Z+1Q1Y/9APqwdLz1JMqMykkh BZZOdRbZE/mTPhzCsqImyyCc7wH0GEhzjy+aSIHE= From: Tomi Valkeinen Date: Wed, 11 Mar 2026 09:48:17 +0200 Subject: [PATCH v2 6/7] drm/bridge: tc358768: Separate video format config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-tc358768-v2-6-e75a99131bd5@ideasonboard.com> References: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> In-Reply-To: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen , =?utf-8?q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4543; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=fGbnE6hMtBI7kYckW9H/SvVRjm5yFP4M95RhcvAmLzQ=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBpsR5T1FA31mXc4KVxP5ToaKNRFLT8Yca4ZHOqR wBANxMcOIWJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCabEeUwAKCRD6PaqMvJYe 9Rb0D/90OBbZ18ZwaFzyYj5l1+HALJt2FNwnf46guycsiNBtUpzpVX+2/KkLrP/M3o+fhmaiMYR 1qiA7JiOOBWa1V4eThaVlH84BtCXMLV0UxiJ85NdVXEvG8HY7S4b3ufIMm1vxggAzZ9eX0CSk8l vIjS34S0gTpWDCKa5NtD7mMew8rn6auzbc9N3A3oS/gFvqwcODml0UKK9pAalgwcP8bR3sdTb5x M18DAQhWjLFwQWTzCbm4nV4q5fpKiTExrKM1joV8MREJJijlTdBNw0JCfwePkMq9svcJXIohp7F an4BVgxyhpa0ySNUh6d45RTOAyQZE+bLOz7YNrrvtJ8r4FJb18/CIjGpff4ueSZmhD4SkwQ/YsE nd8MtpykIplJ4Z24n555u8zORbIc3O1r6i+lv8oK5K0DGrxEISnoByd71fz8J3TjP4rZS1wnvMM fKUPKlLe94eZJEOoCViLtS2/FL+OE8LNsnx3KNPi4IshHBP3UrqZ6/Vx2ddb8As3RjzrWqY4R3H pYd4mBYY0hETJat692RFhzE74LaaFURJYybRl1U3gjr9hXosR9fh4E84qlNMqvH7FFnO6OBepnm jUUj2WN4JJ6AtYWHSe16TRlpeuFhoDBbAcXUtnvG9wtlPEEYKfijNj3tUV66m3AGvl7/IoUIj2/ FCSRf8s8eL66J4g== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Sending long commands using the video buffer (to be implemented in following patches) requires setting TC358768_DATAFMT and TC358768_DSITX_DT registers for command transfer. The same registers also need to be configured properly for video transfer. The long commands will be sent between the bridge's pre_enable() and enable(), and currently we configure the registers for video transfer in pre_enable(). Thus, they would be overwritten by the long command transfer code. To prevent that from happening, set those registers for video transfer in enable(), not in pre_enable(). Based on code from Parth Pancholi Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 51 ++++++++++++++++++++++++++++-------= ---- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a7a14c125ac4..e1ed4003b3c5 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -722,7 +722,7 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; - u32 val, mask, val2, lptxcnt, hact, data_type; + u32 val, mask, val2, lptxcnt, hact; s32 raw_val; struct drm_crtc_state *crtc_state; struct drm_connector_state *conn_state; @@ -768,30 +768,20 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, dsiclk =3D priv->dsiclk; hsbyteclk =3D dsiclk / 4; =20 - /* Data Format Control Register */ - val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ switch (dsi_dev->format) { case MIPI_DSI_FMT_RGB888: - val |=3D (0x3 << 4); hact =3D vm.hactive * 3; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: - val |=3D (0x4 << 4); hact =3D vm.hactive * 3; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: - val |=3D (0x4 << 4) | BIT(3); hact =3D vm.hactive * 18 / 8; - data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: - val |=3D (0x5 << 4); hact =3D vm.hactive * 2; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: dev_err(dev, "Invalid data format (%u)\n", @@ -947,9 +937,6 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, /* VSDly[9:0] */ tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); =20 - tc358768_write(priv, TC358768_DATAFMT, val); - tc358768_write(priv, TC358768_DSITX_DT, data_type); - /* Enable D-PHY (HiZ->LP11) */ tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); /* Enable lanes */ @@ -1113,6 +1100,39 @@ static void tc358768_bridge_atomic_pre_enable(struct= drm_bridge *bridge, dev_err(dev, "Bridge pre_enable failed: %d\n", ret); } =20 +static void tc358768_config_video_format(struct tc358768_priv *priv) +{ + struct mipi_dsi_device *dsi_dev =3D priv->output.dev; + u32 val, data_type; + + /* Data Format Control Register */ + val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ + switch (dsi_dev->format) { + case MIPI_DSI_FMT_RGB888: + val |=3D (0x3 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; + break; + case MIPI_DSI_FMT_RGB666: + val |=3D (0x4 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + val |=3D (0x4 << 4) | BIT(3); + data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; + break; + case MIPI_DSI_FMT_RGB565: + val |=3D (0x5 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; + break; + default: + dev_err(priv->dev, "Invalid data format (%u)\n", dsi_dev->format); + return; + } + + tc358768_write(priv, TC358768_DATAFMT, val); + tc358768_write(priv, TC358768_DSITX_DT, data_type); +} + static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) { @@ -1124,6 +1144,9 @@ static void tc358768_bridge_atomic_enable(struct drm_= bridge *bridge, return; } =20 + /* Configure video format registers */ + tc358768_config_video_format(priv); + /* Enable HS mode for video TX */ tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, TC358768_DSI_CONTROL_TXMD, --=20 2.43.0