From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CDE538F62C for ; Wed, 11 Mar 2026 07:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215326; cv=none; b=VEtMqhYBrFiBExMrjjyJSazm55mctvTyj1BddqiqmoS+pMapenUY7Ewm0rqA/TvPBaDZEYtE3yTHD2G9eTvrDvONNhOx+u05sLuvlEIthgvTmWYXLllVxSGKzLvYyC4bRwCSMCKks+/wymb6vA0z5XFKV9UPrI1Tu0WjO69+CLw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215326; c=relaxed/simple; bh=vBCLbtYgs0zJn8y0zzQ70y9V32mJa46CUHZk8IF/u8c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZR+H4Vu0ZetFINrXOudp1nYzCudTtr+OjD0oAhugaSH/hanCqKQoHvREdHajpH/quP2kTf51UJoroKnR4xr8BE8wkUc69oJjpBX5KNf+BLoGmSvoWyDApzOl3t98G3hkcSobUNvR3pG+JVaBK4si/CHft1dxHqgQYUTARBwF4Dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=IwdIvB++; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="IwdIvB++" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7D3B35A5; Wed, 11 Mar 2026 08:47:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1773215251; bh=vBCLbtYgs0zJn8y0zzQ70y9V32mJa46CUHZk8IF/u8c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IwdIvB++HRbwLFpRu/IazKDcx6MUdnwsJrssO8qybn2l1xb0WLnemDdiYRunNtxzV Ts2f0IRJwSF13l+W7HzpU9SbU/CBYnY/AV+IRoT8CeiNTytie6A3aTYh3Dlyh+bWJb MtDcweVbQeXgDOtddCGAibxoi/tgwzq7DQguDGAc= From: Tomi Valkeinen Date: Wed, 11 Mar 2026 09:48:12 +0200 Subject: [PATCH v2 1/7] drm/bridge: tc358768: Fix typo in TC358768_DSI_CONTROL_DIS_MODE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-tc358768-v2-1-e75a99131bd5@ideasonboard.com> References: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> In-Reply-To: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen , =?utf-8?q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1323; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=vBCLbtYgs0zJn8y0zzQ70y9V32mJa46CUHZk8IF/u8c=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBpsR5RvzJVcUiMXBri/rHnc3Nwh11YCQVIpLGZX rG8zo+bDGeJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCabEeUQAKCRD6PaqMvJYe 9RBtEACXvB8jmwrAKgHYuw1uIxWZ9Cpms8NFqALAmofYPhlYQLy2pyXkNZ0PtcWPYchVME7ULCx 3Jvs2tMifznozMPTHaHkGmVZaORimQ1MHiSaVKNrGjdX1QY+ikulItm+7A35mSOiz16d97+zFr7 OWkEV59tkGenVs8HaQHTHcahqOAgsN+hA7ZDfc4gvJ3D1FSH3ohNBUaMAgwgMfhCbL8RtaryypX UUzJL5eBCxY1JamOsdPCW0OQCpOhq7Rqp1buY0Zm6EpmZ/Hcg0kwADd9Bhl81IhOPra21fOhdaA QW/bEm+bE5DE0oAwZt/gtmDrcoUZIs5GSWIypd8Tpn0uBswoIeEU1OtgQu7ph6GvGnOX0CGJlgD 6kO5KLkBlY4kDWP14e3mvqYFZ5+MAFiEZfx4HSqaF1xDb+MHkAAnVvnsQl64i7D5SH/GFvZLKeo skTGkBOeHglq/5L2ZKc3t5ENgwXjq/Bf2tGcKR/gsxO7S4xKRuDfx8aKkhDnWNOytQFwucbRQ4T dI1gpMlcqFmYVOhmFZ03236x6a9CJiHkOx17vlKg72EB6VvgC8wNHrXLid6M0dPZyFY9AF6lEk/ y+JD+ohdhK8T637m2GXOcfICUD+BgAw7CW7DStupH6qgWPFYuHyReH3QsrQdQ7j2yg3QyRQN9hC 1f8FVf20drMQuIQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 It's "DSI_MODE", not "DIS_MODE". Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index fbdc44e16229..c95d164bd3a0 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -115,7 +115,7 @@ #define TC358768_DSI_HACT 0x062C =20 /* TC358768_DSI_CONTROL (0x040C) register */ -#define TC358768_DSI_CONTROL_DIS_MODE BIT(15) +#define TC358768_DSI_CONTROL_DSI_MODE BIT(15) #define TC358768_DSI_CONTROL_TXMD BIT(7) #define TC358768_DSI_CONTROL_HSCKMD BIT(5) #define TC358768_DSI_CONTROL_EOTDIS BIT(0) @@ -1082,7 +1082,7 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, tc358768_write(priv, TC358768_DSI_CONFW, val); =20 val =3D TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ + val |=3D TC358768_DSI_CONTROL_DSI_MODE; tc358768_write(priv, TC358768_DSI_CONFW, val); =20 ret =3D tc358768_clear_error(priv); --=20 2.43.0 From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84B973B3895 for ; Wed, 11 Mar 2026 07:48:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215334; cv=none; b=bSz1xeNuxXjOGjPGPpTKZRPO2FRI+Zd09Awxyns5viUODzBodFBZOnIKcErXSSeFGQ9g8dqO426yJmYWDUGt3XQV9esDi8f671PKYHscNLsNTndd0tItRw6Zpvx/rqRZXXq2tH2WDYA0UqZPNQJbRIFqC+GsJJRA7pmV270XY1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215334; c=relaxed/simple; bh=4jDT/+odGjD1VSlqBUsEFiTwvxB4MsN/oQwdKaby/IE=; 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Wed, 11 Mar 2026 08:47:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1773215252; bh=4jDT/+odGjD1VSlqBUsEFiTwvxB4MsN/oQwdKaby/IE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nf6MyYyzjMjRdX7gbxuLJDN3zRdKK3rLziSQ6p1VqxmsZl8D8xonZ7huHq99iVZxo H6IamtVA0atdVK/+66ULWaITPnnmj5sSjaFEhazoS0hPZyoh8vRH4Jyg9hTBSnvbMB EFMJgDmVUlglwMUfPM6+021EeuvnKyuYowE5BGKQ= From: Tomi Valkeinen Date: Wed, 11 Mar 2026 09:48:13 +0200 Subject: [PATCH v2 2/7] drm/bridge: tc358768: Set pre_enable_prev_first for reverse order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-tc358768-v2-2-e75a99131bd5@ideasonboard.com> References: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> In-Reply-To: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen , =?utf-8?q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 From: Parth Pancholi Enable the pre_enable_prev_first flag on the tc358768 bridge to reverse the pre-enable order, calling bridge pre_enable before panel prepare. This ensures the bridge is ready before sending panel init commands in the case of panels sending init commands in panel prepare function. Signed-off-by: Parth Pancholi Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index c95d164bd3a0..dab9cdf5cb98 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -448,6 +448,8 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_hos= t *host, DRM_MODE_CONNECTOR_DSI); if (IS_ERR(bridge)) return PTR_ERR(bridge); + + bridge->pre_enable_prev_first =3D true; } =20 priv->output.dev =3D dev; --=20 2.43.0 From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 512E53B389B for ; Wed, 11 Mar 2026 07:48:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="NDB28N8i" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7C286128C; Wed, 11 Mar 2026 08:47:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1773215253; bh=snTnqgApwneclFn8hQMWtvpcYc+LlQ1Ko9atB3hpn8Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NDB28N8ioG2Zqm66RhZsoQx5JWHArMQ4+TgbWZeXZyDcLTX1RrGj5/eobdNZ5fvS/ 0F1Wu/ofRI+s3HK3WiVduevvHrFqy1dE9Wv+StHbqAIic9A58KHIaOwVBjnhndxvG+ JfwvH9EjFmdhB0VFmOYCiaH4hpBfpTZXoBEQ236A= From: Tomi Valkeinen Date: Wed, 11 Mar 2026 09:48:14 +0200 Subject: [PATCH v2 3/7] drm/bridge: tc358768: Separate indirect register writes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Some registers can only be written indirectly, using DSI_CONFW register. We don't have many uses for those registers (in fact, only DSI_CONTROL is currently written), but the code to do those writes inline is a bit confusing. Add a new function, tc358768_confw_update_bits() which can be used to write the bits indirectly. Only DSI_CONTROL is currently supported. Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 52 +++++++++++++++++++++++++++++------= ---- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index dab9cdf5cb98..755ed6483b2e 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -123,7 +123,7 @@ /* TC358768_DSI_CONFW (0x0500) register */ #define TC358768_DSI_CONFW_MODE_SET (5 << 29) #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) -#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) +#define TC358768_DSI_CONFW_ADDR(x) ((x) << 24) =20 /* TC358768_DSICMD_TX (0x0600) register */ #define TC358768_DSI_CMDTX_DC_START BIT(0) @@ -232,6 +232,36 @@ static void tc358768_update_bits(struct tc358768_priv = *priv, u32 reg, u32 mask, tc358768_write(priv, reg, tmp); } =20 +static void tc358768_confw_update_bits(struct tc358768_priv *priv, u16 reg, + u16 mask, u16 val) +{ + u8 confw_addr; + u32 confw_val; + + switch (reg) { + case TC358768_DSI_CONTROL: + confw_addr =3D 0x3; + break; + default: + priv->error =3D -EINVAL; + return; + } + + if (mask !=3D val) { + confw_val =3D TC358768_DSI_CONFW_MODE_CLR | + TC358768_DSI_CONFW_ADDR(confw_addr) | + mask; + tc358768_write(priv, TC358768_DSI_CONFW, confw_val); + } + + if (val & mask) { + confw_val =3D TC358768_DSI_CONFW_MODE_SET | + TC358768_DSI_CONFW_ADDR(confw_addr) | + (val & mask); + tc358768_write(priv, TC358768_DSI_CONFW, confw_val); + } +} + static void tc358768_dsicmd_tx(struct tc358768_priv *priv) { u32 val; @@ -693,7 +723,7 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; unsigned long mode_flags =3D dsi_dev->mode_flags; - u32 val, val2, lptxcnt, hact, data_type; + u32 val, mask, val2, lptxcnt, hact, data_type; s32 raw_val; struct drm_crtc_state *crtc_state; struct drm_connector_state *conn_state; @@ -1065,13 +1095,7 @@ static void tc358768_bridge_atomic_pre_enable(struct= drm_bridge *bridge, tc358768_write(priv, TC358768_DSI_START, 0x1); =20 /* Configure DSI_Control register */ - val =3D TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | - 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; - tc358768_write(priv, TC358768_DSI_CONFW, val); - - val =3D TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D (dsi_dev->lanes - 1) << 1; + val =3D (dsi_dev->lanes - 1) << 1; =20 val |=3D TC358768_DSI_CONTROL_TXMD; =20 @@ -1081,11 +1105,13 @@ static void tc358768_bridge_atomic_pre_enable(struc= t drm_bridge *bridge, if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) val |=3D TC358768_DSI_CONTROL_EOTDIS; =20 - tc358768_write(priv, TC358768_DSI_CONFW, val); + mask =3D TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | + 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; + + tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, mask, val); =20 - val =3D TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; - val |=3D TC358768_DSI_CONTROL_DSI_MODE; - tc358768_write(priv, TC358768_DSI_CONFW, val); + tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, + TC358768_DSI_CONTROL_DSI_MODE, 0); =20 ret =3D tc358768_clear_error(priv); if (ret) --=20 2.43.0 From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C9B269CE6 for ; Wed, 11 Mar 2026 07:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215342; cv=none; b=RhlVxGRH2KhfJTSFEDqybp2Axp8GqnL9ki5VXd8q+Q6kor8qgoOANWF+yRxJuaSC7t6a8nQlfI9iJAX7tjiDz6C+dmKXOAjZZ2klzPNLITnndcR4194Ulx9m71CDw0/i7CitrXSNkhAz8h2Me1KnTZq6XUvN2Qdw2xJOKriCuls= ARC-Message-Signature: i=1; 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Wed, 11 Mar 2026 08:47:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1773215254; bh=b4GVL1v/Wmdcx+qdZ7S2rzI12pbFTYNCd5xdqz222G8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qC4d0qAwGBoPrHTHSjWT657mOVTetfMLdOB+5foww8e9n0Lk9ysZF3iMG3toNknpD S16VRSebZskzhgoydPVuKmf/37BwyFRn62VsMkMt2HlcYfeO9PlCwd7bjKQHsEVFKP kY3cr49UKIM1SMJrKLUr57tDf5ZmO2xLSW1UbYhg= From: Tomi Valkeinen Date: Wed, 11 Mar 2026 09:48:15 +0200 Subject: [PATCH v2 4/7] drm/bridge: tc358768: Support non-continuous clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-tc358768-v2-4-e75a99131bd5@ideasonboard.com> References: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> In-Reply-To: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen , Dmitry Osipenko , =?utf-8?q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 The driver prints a warning if MIPI_DSI_CLOCK_NON_CONTINUOUS is set, and falls back to continuous clock mode. This was added in commit fbc5a90e82c1 ("drm/bridge: tc358768: Disable non-continuous clock mode"). However, there have been multiple changes to the driver since then, and at least in my setup, non-continuous clock mode works: I can see an image on the panel, and I can see the clock lanes being non-continuous with an oscilloscope. So, let's enable MIPI_DSI_CLOCK_NON_CONTINUOUS support. Cc: Dmitry Osipenko Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 755ed6483b2e..a276fbc75dde 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -722,7 +722,6 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; - unsigned long mode_flags =3D dsi_dev->mode_flags; u32 val, mask, val2, lptxcnt, hact, data_type; s32 raw_val; struct drm_crtc_state *crtc_state; @@ -744,11 +743,6 @@ static void tc358768_bridge_atomic_pre_enable(struct d= rm_bridge *bridge, u32 dsi_vsdly; const u32 internal_dly =3D 40; =20 - if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { - dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to c= ontinuous\n"); - mode_flags &=3D ~MIPI_DSI_CLOCK_NON_CONTINUOUS; - } - tc358768_hw_enable(priv); =20 ret =3D tc358768_sw_reset(priv); @@ -1032,7 +1026,7 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, tc358768_write(priv, TC358768_HSTXVREGEN, val); =20 tc358768_write(priv, TC358768_TXOPTIONCNTRL, - (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); + (dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0= )); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); @@ -1099,7 +1093,7 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, =20 val |=3D TC358768_DSI_CONTROL_TXMD; =20 - if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) val |=3D TC358768_DSI_CONTROL_HSCKMD; =20 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) --=20 2.43.0 From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3D923B47C7 for ; Wed, 11 Mar 2026 07:48:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215344; cv=none; b=XL6ifMZnm7W4gHpQLf2XEx0ietZgsPxt5koDARvyj4xN22w1X2Qgg9NuHjB22HYvHcFb5t1N/wclu+0zgNgLhpW8+jx5QMGmE027t/btCaHpXigrZSFL1Ce/9NK2+Zwf9/w9Dp6t6act/VdLmGoHZy8rzPKoXspC16eyJIZGJz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215344; c=relaxed/simple; bh=btFNVPnbDfqc81hXJQ/95BWSk3P/pDV9DN7+Rh/oSI0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Qa35nXTyMBgMat8lHorn6/Eo3Rmdg6Jt4PTgw8XwPhsUM3b/NhCTMIZVLuO4zCLAiJGvYHhFRvTFv4q56YBwQNzNXjisKxt+LGG8FRSQ6hIb7ijqoaP655WWtadv9ynmgkep2d3vgqZb3mSqJP6BD7yVlcl0q0PdovWGfulziEc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=cfwdDB5v; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="cfwdDB5v" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 8C92E12BB; Wed, 11 Mar 2026 08:47:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1773215255; bh=btFNVPnbDfqc81hXJQ/95BWSk3P/pDV9DN7+Rh/oSI0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cfwdDB5v2/v+GTohgNXDGaF2PE+WJr19e2MoaZLd3m7Q+L/92BWIvz8FRPa40CeNR MIpVeYY+6WpC0MSuoBFq3Tzju61oZn+KA2YA+qaxYMGQaOfNz+i2bnqGKH/ctR4Pt2 LE1Lt/oGFqyp9utddUN45zE8oy8XeqhJFdDly9tM= From: Tomi Valkeinen Date: Wed, 11 Mar 2026 09:48:16 +0200 Subject: [PATCH v2 5/7] drm/bridge: tc358768: Add LP mode command support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-tc358768-v2-5-e75a99131bd5@ideasonboard.com> References: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> In-Reply-To: <20260311-tc358768-v2-0-e75a99131bd5@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Parth Pancholi , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen , =?utf-8?q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1553; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=btFNVPnbDfqc81hXJQ/95BWSk3P/pDV9DN7+Rh/oSI0=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBpsR5Tj1wPI6x/AX/8heDBgZA+2rA9UvHW6qDwx K9Zkn6WYkeJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCabEeUwAKCRD6PaqMvJYe 9SH2D/4p3seGtE636J5rbqacWwIlHHKq1KfMQ/cu7+jFsi05poIGT1IAYW7p1xmtMHEGAdePFTu JGLMouosF2fx4WGBkVw03eQt+MCw3Vu5uuoFUdjcOjks4tGHkvhOArgQfq6EuhGbPWwvNOqGKIL ljZzptI+w0oxCb8oaF5ZVkgtwiwKobjsMF1lXLQKSg0KFAMGRuT5zuSNM1BS4XUT0Dbt2qtBZJf 8YfbYrhc54WUW9P6Gp1ZaK8+aRyiRwl1ctzji51YXlAwITmYfbW90Kh6zorDMqSjEgmC8rRjtin F1AdqD1nMstwtwl292kNVWNvFBkkSEnuLkLAjRAjU2cfl29bfBQ0qySRZd9YMiG1YV0Cewjr31l 9mWhEWUmn3BnZTCfWbxGNHH1FiF4wlEf1UwkGEwD7pjItcBLf8s3n7yjA1HTQYgtN13plc3oeEJ wsOO7GSwHjH5lLLk+kGnGy4+qdz96bVdXPhsg/Vgywy0dwKvRpWG5ZGrlWt7oCNOsxud10FYhfk FBJGS6tLgt0otuPNVDArv3V+J4843h2FQi9VVS2kXEyNad5y9zr7SuECCH4DazGUsMdwXw5HYpK PYDxluGbISBb+B4P+RrjkivkcsFkbuagUFkVQmRckzUZt89RMkZqX1kDw8bK4q036KZ06MsPdPN C+rdV8ItzszCF2Q== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Currently the driver ignores MIPI_DSI_MODE_LPM and always uses HS mode. Add code to enable HS mode in pre_enable() only if MIPI_DSI_MODE_LPM is not set, and always enable HS mode in enable() for video transmission. Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a276fbc75dde..a7a14c125ac4 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -1091,7 +1091,8 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, /* Configure DSI_Control register */ val =3D (dsi_dev->lanes - 1) << 1; =20 - val |=3D TC358768_DSI_CONTROL_TXMD; + if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) + val |=3D TC358768_DSI_CONTROL_TXMD; =20 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) val |=3D TC358768_DSI_CONTROL_HSCKMD; @@ -1123,6 +1124,11 @@ static void tc358768_bridge_atomic_enable(struct drm= _bridge *bridge, return; } =20 + /* Enable HS mode for video TX */ + tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, + TC358768_DSI_CONTROL_TXMD, + TC358768_DSI_CONTROL_TXMD); + /* clear FrmStop and RstPtr */ tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); =20 --=20 2.43.0 From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1788A3B47C0 for ; Wed, 11 Mar 2026 07:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215348; cv=none; b=kxxcIpUa2le13BD2KfoMg5KfAh820LBYTp4HuFej3ztoyyjP/Y8dBEeCiPlyOUMh6V/V4xIwYCyV4Jq/08DSYWwT9njpBVjekRJuRWdD9kvL0cMsGEpQfxlLgUEOlRavDAFY95QHKK4Ln2bl2UboBZr+SEjBkqMIB15nhiPuToo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215348; c=relaxed/simple; bh=fGbnE6hMtBI7kYckW9H/SvVRjm5yFP4M95RhcvAmLzQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Sending long commands using the video buffer (to be implemented in following patches) requires setting TC358768_DATAFMT and TC358768_DSITX_DT registers for command transfer. The same registers also need to be configured properly for video transfer. The long commands will be sent between the bridge's pre_enable() and enable(), and currently we configure the registers for video transfer in pre_enable(). Thus, they would be overwritten by the long command transfer code. To prevent that from happening, set those registers for video transfer in enable(), not in pre_enable(). Based on code from Parth Pancholi Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 51 ++++++++++++++++++++++++++++-------= ---- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a7a14c125ac4..e1ed4003b3c5 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -722,7 +722,7 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev =3D priv->output.dev; - u32 val, mask, val2, lptxcnt, hact, data_type; + u32 val, mask, val2, lptxcnt, hact; s32 raw_val; struct drm_crtc_state *crtc_state; struct drm_connector_state *conn_state; @@ -768,30 +768,20 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, dsiclk =3D priv->dsiclk; hsbyteclk =3D dsiclk / 4; =20 - /* Data Format Control Register */ - val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ switch (dsi_dev->format) { case MIPI_DSI_FMT_RGB888: - val |=3D (0x3 << 4); hact =3D vm.hactive * 3; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: - val |=3D (0x4 << 4); hact =3D vm.hactive * 3; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: - val |=3D (0x4 << 4) | BIT(3); hact =3D vm.hactive * 18 / 8; - data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: - val |=3D (0x5 << 4); hact =3D vm.hactive * 2; - data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: dev_err(dev, "Invalid data format (%u)\n", @@ -947,9 +937,6 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, /* VSDly[9:0] */ tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); =20 - tc358768_write(priv, TC358768_DATAFMT, val); - tc358768_write(priv, TC358768_DSITX_DT, data_type); - /* Enable D-PHY (HiZ->LP11) */ tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); /* Enable lanes */ @@ -1113,6 +1100,39 @@ static void tc358768_bridge_atomic_pre_enable(struct= drm_bridge *bridge, dev_err(dev, "Bridge pre_enable failed: %d\n", ret); } =20 +static void tc358768_config_video_format(struct tc358768_priv *priv) +{ + struct mipi_dsi_device *dsi_dev =3D priv->output.dev; + u32 val, data_type; + + /* Data Format Control Register */ + val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ + switch (dsi_dev->format) { + case MIPI_DSI_FMT_RGB888: + val |=3D (0x3 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; + break; + case MIPI_DSI_FMT_RGB666: + val |=3D (0x4 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + val |=3D (0x4 << 4) | BIT(3); + data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; + break; + case MIPI_DSI_FMT_RGB565: + val |=3D (0x5 << 4); + data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; + break; + default: + dev_err(priv->dev, "Invalid data format (%u)\n", dsi_dev->format); + return; + } + + tc358768_write(priv, TC358768_DATAFMT, val); + tc358768_write(priv, TC358768_DSITX_DT, data_type); +} + static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) { @@ -1124,6 +1144,9 @@ static void tc358768_bridge_atomic_enable(struct drm_= bridge *bridge, return; } =20 + /* Configure video format registers */ + tc358768_config_video_format(priv); + /* Enable HS mode for video TX */ tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, TC358768_DSI_CONTROL_TXMD, --=20 2.43.0 From nobody Tue Apr 7 00:50:51 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708B63B47D7 for ; Wed, 11 Mar 2026 07:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 TC358768 has two ways to send DSI commands: 1) buffer the payload data into registers (DSICMD_WDx), which supports up to 8 bytes of payload, 2) buffer the payload data into the video buffer, which supports up to 1024 bytes of payload. The driver currently supports method 1). Add support for transmitting long DSI commands (more than 8 bytes, up to 1024 bytes) using the video buffer. This mode can only be used before the actual video transmission is enabled, i.e. the initial configuration. Original version from Parth Pancholi Tested-by: Jo=C3=A3o Paulo Gon=C3=A7alves # To= radex Verdin AM62 Reviewed-by: Francesco Dolcini Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 79 ++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index e1ed4003b3c5..e0b5a4b5abbe 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -45,6 +45,9 @@ =20 /* Debug (16-bit addressable) */ #define TC358768_VBUFCTRL 0x00E0 +#define TC358768_VBUFCTRL_VBUF_EN BIT(15) +#define TC358768_VBUFCTRL_TX_EN BIT(14) +#define TC358768_VBUFCTRL_MASK BIT(13) #define TC358768_DBG_WIDTH 0x00E2 #define TC358768_DBG_VBLANK 0x00E4 #define TC358768_DBG_DATA 0x00E8 @@ -537,9 +540,21 @@ static ssize_t tc358768_dsi_host_transfer(struct mipi_= dsi_host *host, return -ENOTSUPP; } =20 + if (msg->tx_len > 1024) { + dev_warn(priv->dev, "Maximum 1024 byte MIPI tx is supported\n"); + return -EINVAL; + } + if (msg->tx_len > 8) { - dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); - return -ENOTSUPP; + u32 confctl; + + tc358768_read(priv, TC358768_CONFCTL, &confctl); + + if (confctl & BIT(6)) { + dev_warn(priv->dev, + "Video is currently active. Unable to transmit long command\n"); + return -EBUSY; + } } =20 ret =3D mipi_dsi_create_packet(&packet, msg); @@ -552,23 +567,66 @@ static ssize_t tc358768_dsi_host_transfer(struct mipi= _dsi_host *host, tc358768_write(priv, TC358768_DSICMD_WC, 0); tc358768_write(priv, TC358768_DSICMD_WD0, (packet.header[2] << 8) | packet.header[1]); - } else { - int i; - + tc358768_dsicmd_tx(priv); + } else if (packet.payload_length <=3D 8) { tc358768_write(priv, TC358768_DSICMD_TYPE, (0x40 << 8) | (packet.header[0] & 0x3f)); tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); - for (i =3D 0; i < packet.payload_length; i +=3D 2) { + + for (int i =3D 0; i < packet.payload_length; i +=3D 2) { u16 val =3D packet.payload[i]; =20 if (i + 1 < packet.payload_length) val |=3D packet.payload[i + 1] << 8; - tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); } - } =20 - tc358768_dsicmd_tx(priv); + tc358768_dsicmd_tx(priv); + } else { + unsigned long tx_sleep_us; + size_t len; + + /* For packets over 8 bytes we need to use the video buffer */ + tc358768_write(priv, TC358768_DATAFMT, BIT(0)); /* txdt_en */ + tc358768_write(priv, TC358768_DSITX_DT, packet.header[0] & 0x3f); + tc358768_write(priv, TC358768_CMDBYTE, packet.payload_length); + tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_VBUF_EN); + + /* + * Write the payload in 2-byte chunks, and pad with zeroes to + * align to 4 bytes. + */ + len =3D ALIGN(packet.payload_length, 4); + + for (int i =3D 0; i < len; i +=3D 2) { + u16 val =3D 0; + + if (i < packet.payload_length) + val |=3D packet.payload[i]; + if (i + 1 < packet.payload_length) + val |=3D packet.payload[i + 1] << 8; + + tc358768_write(priv, TC358768_DBG_DATA, val); + } + + /* Start transmission */ + tc358768_write(priv, TC358768_VBUFCTRL, + TC358768_VBUFCTRL_VBUF_EN | + TC358768_VBUFCTRL_TX_EN | + TC358768_VBUFCTRL_MASK); + + /* + * The TC358768 spec says to wait until the transmission has + * been finished, estimating the sleep time based on the payload + * and clock rates. We use a simple safe estimate of 2us per + * byte (LP mode transmission). + */ + tx_sleep_us =3D packet.payload_length * 2; + usleep_range(tx_sleep_us, tx_sleep_us * 2); + + tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_MASK); + tc358768_write(priv, TC358768_VBUFCTRL, 0); /* Stop transmission */ + } =20 ret =3D tc358768_clear_error(priv); if (ret) @@ -752,6 +810,9 @@ static void tc358768_bridge_atomic_pre_enable(struct dr= m_bridge *bridge, return; } =20 + /* Release RstPtr so that the video buffer can be used for DSI commands */ + tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), 0); + connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); conn_state =3D drm_atomic_get_new_connector_state(state, connector); crtc_state =3D drm_atomic_get_new_crtc_state(state, conn_state->crtc); --=20 2.43.0