From nobody Thu Apr 2 18:47:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3D1931B803; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235635; cv=none; b=BJbHwNZzvvIf0meX9cwJgqqzdFO1g7y/osefL1mZhqIE56jt3OCoolnVtI/ZBfrgfcjc3eC++xELXM11p/H+XMRglqeWbAPxY3Cm7J60ixSqorzyJNozidU7ZX65DuG5VUs6zJwijmUo/Be/CLU/EnIymB3DW3oH3dHp3mJZ3gc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235635; c=relaxed/simple; bh=LFbmUOex4B5o7clfZWmgNVfvHIxLuigp4QSkfd7cb74=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YO+NEmZfzqyIxupWyQE1sIKZWq6AI8Msjq2MvtPzkUsmaBIuRstCInGfKjltLukAzM6Ob6XfA8Fj5s2TD1GdlLkDvgLN9vAnNpe0WMq7aXWnhSb0CsR+UxWIoS0ASK+K7vCWa73bTrC+GOhImYbJ7PedTIC8iEDh1GAPHSfhAN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nbAbFYXR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nbAbFYXR" Received: by smtp.kernel.org (Postfix) with ESMTPS id B3D5EC2BCB3; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773235634; bh=LFbmUOex4B5o7clfZWmgNVfvHIxLuigp4QSkfd7cb74=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nbAbFYXR8sLu7zXHPc+et0xJU6Zt3V1v+UhtA8sIc95xaU2+jnxwqHroK72AeU/lD ooAEIZWecHoRNy3lmMnkQef2iVSlOzL9aBfF4mGsmWyWXUByd29RAKqU2mzfkdtt8U jgdmNZDCk1BvxP2V43JI7CIfm+Y98ZVW+QFWdgkEqJE8+XSM0U/FBeUU66AsCPD54N 4ODRWXGkPSYvXHBw0MND9izyIVgEPsqkyyu9a7Lm1noEuajGVl7zfLY/m4sgrVo04a 0VvDL2W8WtVgL0auOqXnyL1hzv3MLImiH+5J0ug8lRXQ0ZwPIurHPjLwcDXOUXok+g ZBr2GPuvRcsXg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC95D112580C; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 11 Mar 2026 14:26:57 +0100 Subject: [PATCH v7 3/3] riscv: clocksource: Add p8700-gcru driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-riscv-time-mmio-v7-3-016845a0f808@htecgroup.com> References: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> In-Reply-To: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773235633; l=3250; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=6tKjaKViZn8P2amTu2oO3Kpu4d2sX/LUMZ6acjvMpRY=; b=fXcnagy2tx3oaD+njlXo1rWkaoWBHFQgCroBxs+y6LbN7XHocxSoVYCuv7strvmSP1AcZNlWi j5sqN9fNhp2CKQvw+xGRxXNvfIJIJRRYdaBA08SUZQ0/Bmve3zeJ+mv X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add a clocksource driver for the P8700 GCRU. Initialization uses helper functions provided by clocksource/mmio.c and timer-of.c. Since the GCRU does not support any kind of interrupts, the default RISC-V clockevent implementation should suffice. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/Kconfig | 9 ++++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-p8700.c | 45 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 55 insertions(+) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ffcd23668763fe7707a4e917bf240caadbb09a8c..861e7b8c93376b345e3a488dabe= 435d06a42f357 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -672,6 +672,15 @@ config CLINT_TIMER This option enables the CLINT timer for RISC-V systems. The CLINT driver is usually used for NoMMU RISC-V systems. =20 +config P8700_TIMER + bool "MIPS P8700 timer driver" + depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI + select CLKSRC_MMIO + select TIMER_PROBE + select TIMER_OF + help + Enables support for MIPS P8700 timer driver. + config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ec4452ee958f1a814c708aeba6412bea61d24892..fae9a58d6c8663a7c857b9ab7fd= ae05782b3551c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -95,3 +95,4 @@ obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) +=3D timer-loongson1-p= wm.o obj-$(CONFIG_EP93XX_TIMER) +=3D timer-ep93xx.o obj-$(CONFIG_RALINK_TIMER) +=3D timer-ralink.o obj-$(CONFIG_NXP_STM_TIMER) +=3D timer-nxp-stm.o +obj-$(CONFIG_P8700_TIMER) +=3D timer-p8700.o diff --git a/drivers/clocksource/timer-p8700.c b/drivers/clocksource/timer-= p8700.c new file mode 100644 index 0000000000000000000000000000000000000000..220ed8efdfe5544a3f925ad43b8= faf2e0565557b --- /dev/null +++ b/drivers/clocksource/timer-p8700.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +static struct timer_of gcru_of =3D { .flags =3D TIMER_OF_BASE }; +static u64 __iomem *p8700_time_val __ro_after_init; + +static u64 notrace p8700_timer_sched_read(void) +{ + return (u64)readq_relaxed(p8700_time_val); +} + +static int __init p8700_timer_init(struct device_node *node) +{ + int error =3D 0; + + error =3D timer_of_init(node, &gcru_of); + if (error) + return error; + + p8700_time_val =3D timer_of_base(&gcru_of); + /* Now init the mmio timer with the address we got from DT */ + error =3D clocksource_mmio_init(p8700_time_val, "mips,p8700-gcru", + riscv_timebase, 450, 64, + clocksource_mmio_readq_up); + if (error) + return error; + + /* Sched clock */ + sched_clock_register(p8700_timer_sched_read, 64, riscv_timebase); + + return error; +} + +TIMER_OF_DECLARE(p8700_timer, "mips,p8700-gcru", p8700_timer_init); --=20 2.43.0