From nobody Thu Apr 2 18:49:17 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE68131AABC; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235634; cv=none; b=G5drefFRDOAeVOYfPIR9DAF+0gucOc+wNnlj33gzbMakun8q3MAIfx/JYRPNmlx7Qzj3iWi6J/dPAj0c61M6AtwNCt7bOdjQxBXp18wcSZxWYdyu5L9pOZVPk69KHF8emnHjkwqWCg7P0rrRxn/odVazEEDpixyB8FAjSXLsuVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235634; c=relaxed/simple; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a8etdtYnaCdxn76FounqK2bxELfRTIQeVVygvBXlZAKBzgN8MaWVObJLH3UmIvW/pzeD648UE96QI9Cr0SpTEv5g+fEcaSqq9GE9L6iuUoojrjMZC4ZgecLc2eJ+oOiTyuBkn3iztg7jVenwaS/32cAn+yHcNGYqQgYrGXWC2RM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rf27pbZ3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rf27pbZ3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9A504C2BC9E; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773235634; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rf27pbZ34+j3kG9NcUHKvgga+r6vxTo4JxVSuWJ135F1q4yLfwkePdSIFNN4W4kGs J4wI0Ga+4+DDLqikNg3LiGWPyFNViBQIYTcfivC1zoZusDsIILxEpmf3K1EPB1w9N3 e+hAsQiqAve/+ZMiJ03uvAKYxANc6WY/xKk09GqXczAAPvVR+B2Y4wRhP96REfEkcI 5HyQzwK48h9lWmY3ZmZlHScar4sb5bIM37AZf+BbbwDqlUEbXHLI73RZIKPKB/ns2f 6Psw3gGZKcBkDhqZtFRLuotoCyeUAPysq18tnUoNLq7wDf85GXSwYXpTqGcfZGOElJ 1j6NcYvn8Xeuw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B6881125809; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 11 Mar 2026 14:26:55 +0100 Subject: [PATCH v7 1/3] dt-bindings: timer: mips,p8700-gcru Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-riscv-time-mmio-v7-1-016845a0f808@htecgroup.com> References: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> In-Reply-To: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773235633; l=1839; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=qlCmLDBO1Y2Dd5pfYZ/Ggi2QMtMAGxo3h0341eF3VPk=; b=U4M3KAsGzL2iGmEylw5kFQRQqxOoijFTGZzePXyl2kKy4iv9SCwrk+Gig4NjUET9fNWjVbJo6 Pf5eiGGyYSyCLHIqHmJoKJOpoog/t+2tBexrtuBhYJp97YMse1WzeKQ X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add dt-bindings for the GCR.U memory mapped timer device for RISC-V platforms. The GCR.U memory region contains shadow copies of the RISC-V mtime register and the hrtime Global Configuration Register. Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley --- .../devicetree/bindings/timer/mips,p8700-gcru.yaml | 38 ++++++++++++++++++= ++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml b= /Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3498255762cce6b3f491292d340= d9639bb573e6d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mips,p8700-gcru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GCR.U timer device for the MIPS P8700 platform + +maintainers: + - Aleksa Paunovic + +description: + The GCR.U memory region contains memory mapped shadow copies of + mtime and hrtime Global Configuration Registers, + which software can choose to make accessible from user mode. + +properties: + compatible: + const: mips,p8700-gcru + + reg: + items: + - description: Read-only shadow copy of the RISC-V mtime register. + - description: Read-only shadow copy of the P8700 high resolution ti= mer register. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + timer@1617f000 { + compatible =3D "mips,p8700-gcru"; + reg =3D <0x1617f050 0x8>, + <0x1617f090 0x8>; + }; --=20 2.43.0