From nobody Thu Apr 2 17:14:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE68131AABC; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235634; cv=none; b=G5drefFRDOAeVOYfPIR9DAF+0gucOc+wNnlj33gzbMakun8q3MAIfx/JYRPNmlx7Qzj3iWi6J/dPAj0c61M6AtwNCt7bOdjQxBXp18wcSZxWYdyu5L9pOZVPk69KHF8emnHjkwqWCg7P0rrRxn/odVazEEDpixyB8FAjSXLsuVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235634; c=relaxed/simple; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a8etdtYnaCdxn76FounqK2bxELfRTIQeVVygvBXlZAKBzgN8MaWVObJLH3UmIvW/pzeD648UE96QI9Cr0SpTEv5g+fEcaSqq9GE9L6iuUoojrjMZC4ZgecLc2eJ+oOiTyuBkn3iztg7jVenwaS/32cAn+yHcNGYqQgYrGXWC2RM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rf27pbZ3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rf27pbZ3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9A504C2BC9E; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773235634; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rf27pbZ34+j3kG9NcUHKvgga+r6vxTo4JxVSuWJ135F1q4yLfwkePdSIFNN4W4kGs J4wI0Ga+4+DDLqikNg3LiGWPyFNViBQIYTcfivC1zoZusDsIILxEpmf3K1EPB1w9N3 e+hAsQiqAve/+ZMiJ03uvAKYxANc6WY/xKk09GqXczAAPvVR+B2Y4wRhP96REfEkcI 5HyQzwK48h9lWmY3ZmZlHScar4sb5bIM37AZf+BbbwDqlUEbXHLI73RZIKPKB/ns2f 6Psw3gGZKcBkDhqZtFRLuotoCyeUAPysq18tnUoNLq7wDf85GXSwYXpTqGcfZGOElJ 1j6NcYvn8Xeuw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B6881125809; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 11 Mar 2026 14:26:55 +0100 Subject: [PATCH v7 1/3] dt-bindings: timer: mips,p8700-gcru Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-riscv-time-mmio-v7-1-016845a0f808@htecgroup.com> References: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> In-Reply-To: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773235633; l=1839; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=qlCmLDBO1Y2Dd5pfYZ/Ggi2QMtMAGxo3h0341eF3VPk=; b=U4M3KAsGzL2iGmEylw5kFQRQqxOoijFTGZzePXyl2kKy4iv9SCwrk+Gig4NjUET9fNWjVbJo6 Pf5eiGGyYSyCLHIqHmJoKJOpoog/t+2tBexrtuBhYJp97YMse1WzeKQ X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add dt-bindings for the GCR.U memory mapped timer device for RISC-V platforms. The GCR.U memory region contains shadow copies of the RISC-V mtime register and the hrtime Global Configuration Register. Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley --- .../devicetree/bindings/timer/mips,p8700-gcru.yaml | 38 ++++++++++++++++++= ++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml b= /Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3498255762cce6b3f491292d340= d9639bb573e6d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mips,p8700-gcru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GCR.U timer device for the MIPS P8700 platform + +maintainers: + - Aleksa Paunovic + +description: + The GCR.U memory region contains memory mapped shadow copies of + mtime and hrtime Global Configuration Registers, + which software can choose to make accessible from user mode. + +properties: + compatible: + const: mips,p8700-gcru + + reg: + items: + - description: Read-only shadow copy of the RISC-V mtime register. + - description: Read-only shadow copy of the P8700 high resolution ti= mer register. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + timer@1617f000 { + compatible =3D "mips,p8700-gcru"; + reg =3D <0x1617f050 0x8>, + <0x1617f090 0x8>; + }; --=20 2.43.0 From nobody Thu Apr 2 17:14:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE60531AAAF; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235634; cv=none; b=Jym+0/dMi/ve3xv56QhOfCXmWMrHJPJABTNzmksr/JQ7e1Sz4jseKLlmcUmt49KbC23b+CIFXeiX+6pAc1JNz5kTLghdWgoFOA8wSDz36muFnxPmkDhmdV5KUJLHOnmjgJeFc8nc/zpKxIZpkmdG7MileVvTd3UsvsuKhhNeQng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235634; c=relaxed/simple; bh=41IZMqDKuz/6MXeNloPVlflrmSHQD4lgmzdF8Vzr3C4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fDyDrqwsST7kxiJJ7PGbW2/YkccsHqvQFQkl5tIkdRu/hYQkA3TiDtg5VTbqNf507lxw/znym9ZBLBJ/kP3DyABZ7jwoQBrgHisHrxwZyM4QAR4zJaDJ1ps2ZwMscyWELomACtalq1Gckvq3M6mtqbngDSs+2fnW/xFlWcHZ5yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Wg/z9oGZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Wg/z9oGZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id AB58FC2BCB0; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773235634; bh=41IZMqDKuz/6MXeNloPVlflrmSHQD4lgmzdF8Vzr3C4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Wg/z9oGZMQ8Upk/M9sxd5UvjPLn3ccHGiMNUqptULOJmMxWo/9iPpOxqM/oNjprSR XLmF4iO9tjRGo1ITdUgB3Mk8bdYTH6ya9EUi7i3yzyS66JwM4UVFKzR/eK95uIsFXC EWDLYNwQEPjawSucVdg7VP9/PNXVATwDn30CH2zaPs4tXzKonOUVXcufMY4f4pydtV HRYtrPvfXRGx7/09B1kWB5vVian6MwsHH4G9DNLMA7/iSTzJDHWnj6rGmF3mDxeSqs HeqRljlRq6yH1tDKnWx8hoiiCV5ulpCTWFxSRKSwMqai6ItkfVzilB5YCIVNVEP4Eu AswkVwvkivFhw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C9561125808; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 11 Mar 2026 14:26:56 +0100 Subject: [PATCH v7 2/3] riscv: clocksource: Add readq options to clocksource mmio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-riscv-time-mmio-v7-2-016845a0f808@htecgroup.com> References: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> In-Reply-To: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773235633; l=1888; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=Jv3vpBN1+Uh24vJH4CQZDSOQFXoXTNQJWJ4G2f0Tyms=; b=Wm4pnQNuSaGPFUBpuq6TtRUM/iSnjVcf5KngdyLUNX4MMZ1f/TyMH1XPBLeEXuSw7VHoGZkdj 61dIQnhqjloANjTX9T3btPV0/UEGZ1kT1f/te1W2lVdqHqZ3+XBWhnj X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add read functions for 64-bit register size to the generic mmio clocksource, covering both up and down counters. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/mmio.c | 14 ++++++++++++++ include/linux/clocksource.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c index 9de75153183124cc8997c6ab61d0c01d9b2637bc..6329d8ce2c0911b5c6de34346b5= ca8de40b93099 100644 --- a/drivers/clocksource/mmio.c +++ b/drivers/clocksource/mmio.c @@ -17,6 +17,20 @@ static inline struct clocksource_mmio *to_mmio_clksrc(st= ruct clocksource *c) return container_of(c, struct clocksource_mmio, clksrc); } =20 +#if defined(readq_relaxed) + +u64 clocksource_mmio_readq_up(struct clocksource *c) +{ + return (u64)readq_relaxed(to_mmio_clksrc(c)->reg); +} + +u64 clocksource_mmio_readq_down(struct clocksource *c) +{ + return ~(u64)readq_relaxed(to_mmio_clksrc(c)->reg) & c->mask; +} + +#endif + u64 clocksource_mmio_readl_up(struct clocksource *c) { return (u64)readl_relaxed(to_mmio_clksrc(c)->reg); diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 65b7c41471c390463770c2da13694e58e83b84ea..df8ea45ec60a28e0276020cb95a= b5328bec89879 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -276,6 +276,10 @@ static inline void clocksource_arch_init(struct clocks= ource *cs) { } =20 extern int timekeeping_notify(struct clocksource *clock); =20 +#if defined(readq_relaxed) +extern u64 clocksource_mmio_readq_up(struct clocksource *c); +extern u64 clocksource_mmio_readq_down(struct clocksource *c); +#endif extern u64 clocksource_mmio_readl_up(struct clocksource *); extern u64 clocksource_mmio_readl_down(struct clocksource *); extern u64 clocksource_mmio_readw_up(struct clocksource *); --=20 2.43.0 From nobody Thu Apr 2 17:14:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3D1931B803; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235635; cv=none; b=BJbHwNZzvvIf0meX9cwJgqqzdFO1g7y/osefL1mZhqIE56jt3OCoolnVtI/ZBfrgfcjc3eC++xELXM11p/H+XMRglqeWbAPxY3Cm7J60ixSqorzyJNozidU7ZX65DuG5VUs6zJwijmUo/Be/CLU/EnIymB3DW3oH3dHp3mJZ3gc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773235635; c=relaxed/simple; bh=LFbmUOex4B5o7clfZWmgNVfvHIxLuigp4QSkfd7cb74=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YO+NEmZfzqyIxupWyQE1sIKZWq6AI8Msjq2MvtPzkUsmaBIuRstCInGfKjltLukAzM6Ob6XfA8Fj5s2TD1GdlLkDvgLN9vAnNpe0WMq7aXWnhSb0CsR+UxWIoS0ASK+K7vCWa73bTrC+GOhImYbJ7PedTIC8iEDh1GAPHSfhAN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nbAbFYXR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nbAbFYXR" Received: by smtp.kernel.org (Postfix) with ESMTPS id B3D5EC2BCB3; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773235634; bh=LFbmUOex4B5o7clfZWmgNVfvHIxLuigp4QSkfd7cb74=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nbAbFYXR8sLu7zXHPc+et0xJU6Zt3V1v+UhtA8sIc95xaU2+jnxwqHroK72AeU/lD ooAEIZWecHoRNy3lmMnkQef2iVSlOzL9aBfF4mGsmWyWXUByd29RAKqU2mzfkdtt8U jgdmNZDCk1BvxP2V43JI7CIfm+Y98ZVW+QFWdgkEqJE8+XSM0U/FBeUU66AsCPD54N 4ODRWXGkPSYvXHBw0MND9izyIVgEPsqkyyu9a7Lm1noEuajGVl7zfLY/m4sgrVo04a 0VvDL2W8WtVgL0auOqXnyL1hzv3MLImiH+5J0ug8lRXQ0ZwPIurHPjLwcDXOUXok+g ZBr2GPuvRcsXg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC95D112580C; Wed, 11 Mar 2026 13:27:14 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 11 Mar 2026 14:26:57 +0100 Subject: [PATCH v7 3/3] riscv: clocksource: Add p8700-gcru driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-riscv-time-mmio-v7-3-016845a0f808@htecgroup.com> References: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> In-Reply-To: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773235633; l=3250; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=6tKjaKViZn8P2amTu2oO3Kpu4d2sX/LUMZ6acjvMpRY=; b=fXcnagy2tx3oaD+njlXo1rWkaoWBHFQgCroBxs+y6LbN7XHocxSoVYCuv7strvmSP1AcZNlWi j5sqN9fNhp2CKQvw+xGRxXNvfIJIJRRYdaBA08SUZQ0/Bmve3zeJ+mv X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add a clocksource driver for the P8700 GCRU. Initialization uses helper functions provided by clocksource/mmio.c and timer-of.c. Since the GCRU does not support any kind of interrupts, the default RISC-V clockevent implementation should suffice. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/Kconfig | 9 ++++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-p8700.c | 45 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 55 insertions(+) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ffcd23668763fe7707a4e917bf240caadbb09a8c..861e7b8c93376b345e3a488dabe= 435d06a42f357 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -672,6 +672,15 @@ config CLINT_TIMER This option enables the CLINT timer for RISC-V systems. The CLINT driver is usually used for NoMMU RISC-V systems. =20 +config P8700_TIMER + bool "MIPS P8700 timer driver" + depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI + select CLKSRC_MMIO + select TIMER_PROBE + select TIMER_OF + help + Enables support for MIPS P8700 timer driver. + config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ec4452ee958f1a814c708aeba6412bea61d24892..fae9a58d6c8663a7c857b9ab7fd= ae05782b3551c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -95,3 +95,4 @@ obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) +=3D timer-loongson1-p= wm.o obj-$(CONFIG_EP93XX_TIMER) +=3D timer-ep93xx.o obj-$(CONFIG_RALINK_TIMER) +=3D timer-ralink.o obj-$(CONFIG_NXP_STM_TIMER) +=3D timer-nxp-stm.o +obj-$(CONFIG_P8700_TIMER) +=3D timer-p8700.o diff --git a/drivers/clocksource/timer-p8700.c b/drivers/clocksource/timer-= p8700.c new file mode 100644 index 0000000000000000000000000000000000000000..220ed8efdfe5544a3f925ad43b8= faf2e0565557b --- /dev/null +++ b/drivers/clocksource/timer-p8700.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +static struct timer_of gcru_of =3D { .flags =3D TIMER_OF_BASE }; +static u64 __iomem *p8700_time_val __ro_after_init; + +static u64 notrace p8700_timer_sched_read(void) +{ + return (u64)readq_relaxed(p8700_time_val); +} + +static int __init p8700_timer_init(struct device_node *node) +{ + int error =3D 0; + + error =3D timer_of_init(node, &gcru_of); + if (error) + return error; + + p8700_time_val =3D timer_of_base(&gcru_of); + /* Now init the mmio timer with the address we got from DT */ + error =3D clocksource_mmio_init(p8700_time_val, "mips,p8700-gcru", + riscv_timebase, 450, 64, + clocksource_mmio_readq_up); + if (error) + return error; + + /* Sched clock */ + sched_clock_register(p8700_timer_sched_read, 64, riscv_timebase); + + return error; +} + +TIMER_OF_DECLARE(p8700_timer, "mips,p8700-gcru", p8700_timer_init); --=20 2.43.0