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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df5ff0sm1677403b3a.21.2026.03.11.02.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 02:46:39 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 11 Mar 2026 15:15:50 +0530 Subject: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ipq5210_boot_to_shell-v1-8-fe857d68d698@oss.qualcomm.com> References: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> In-Reply-To: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Linus Walleij , Konrad Dybcio , Ulf Hansson , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mmc@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773222347; l=10487; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=dlSRQRF023jUCsl4IbZQYSPJTNojRWXNTDfxc219h60=; b=qIko03d3wIkBuaJSeXL1R9YQKDCjfVPfJVR4ZnzgiUwI6+6g9dbjOoTKOItDFJ4JJ9SbEo2MR Q+O+XozkBTODSw38ebYhPY+EpvoEuDKPoxjEHDBoigTr+Y3rArztMz8 X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4MSBTYWx0ZWRfX/cKYLoAarv3N dGP5Ol8LL8kOovdcWUCFVgiEzNZO9YPZFjRg46rYjyb070Q1rIy6KTbH/RDektbxaG3jEwHNFQQ dpVWBAlBeOXRdIL4DoC4gmzGWTVVgJZF0QJ/lI9diL5jSH/scVutOHPiNGE/5OZZMFoBBwW4PV8 LUlo+TZx8Ps8c+gzG3NiWEIndNSGS4A/+oQWLVzAbyuiWkrxFmstHwYMk3/iCp9Ab4bPZRJmOYh UqUV0XCB+eB2/erk8yD5pXEsbwJzydAhFFbif+18+SeUpQlBmvyeAu2K6+h1fmnwlW1k/kK+h+c UBJCjO6uYiILJVO8GD+sjMkcT/iE9l/VU0v+iBQLZ2Mu9o0ogTbihpd4GnQG3oUXOOymkV8xSNc i+4E5lc9EZJAfcxgbF+mWHoDup1MzphCLjTJINfIBWP02XrUGNpSBknOSF7M2espAf9RjuPVkHH RrXmjeDtfgEWtn47mpQ== X-Proofpoint-ORIG-GUID: iRc-f8-dtHPf2r9K7v8BKIDdf0Pe5S3D X-Authority-Analysis: v=2.4 cv=Lo2fC3dc c=1 sm=1 tr=0 ts=69b13a01 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=fBkTXTPqfNaV2XDYC8MA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: iRc-f8-dtHPf2r9K7v8BKIDdf0Pe5S3D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110081 Add initial device tree support for the Qualcomm IPQ5210 SoC and rdp504 board. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 ++++++++++++++++++++++++= ++++ 3 files changed, 398 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37= aa441444c2b13 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs :=3D hamoa-iot-evk.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5210-rdp504.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts new file mode 100644 index 0000000000000000000000000000000000000000..3d95939785bc5bd4f510e2f992f= 0a1e80848c8de --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + compatible =3D "qcom,ipq5210-rdp504", "qcom,ipq5210"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0"; + }; + + soc@0 { + qupv3: geniqup@1ac0000 { + status =3D "okay"; + + uart1: serial@1a84000 { + pinctrl-0 =3D <&qup_uart1_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; + }; + }; + }; +}; + +&sdhc { + max-frequency =3D <192000000>; + bus-width =3D <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 =3D <&sdhc_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + tx-pins { + pins =3D "gpio39"; + function =3D "qup_se1_l2"; + drive-strength =3D <6>; + bias-pull-down; + }; + + rx-pins { + pins =3D "gpio38"; + function =3D "qup_se1_l3"; + drive-strength =3D <6>; + bias-pull-down; + }; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; +}; + +&xo { + clock-frequency =3D <24000000>; +}; + diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b959162737c87d8c44fd18cd7e9= 54f85f797085a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo: xo { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + L2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <0x2>; + cache-unified; + }; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scm { + compatible =3D "qcom,scm-ipq5210", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + bootloader@87800000 { + reg =3D <0x0 0x87800000 0x0 0x400000>; + no-map; + }; + + smem@87c00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x87c00000 0x0 0x40000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + tfa@87d00000 { + reg =3D <0x0 0x87d00000 0x0 0x80000>; + no-map; + }; + + optee@87d80000 { + reg =3D <0x0 0x87d80000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq5210-tlmm"; + reg =3D <0x0 0x01000000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq5210-gcc"; + reg =3D <0x0 0x01800000 0x0 0x40000>; + clocks =3D <&xo>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01905000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + status =3D "disabled"; + + uart1: serial@1a84000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_SE1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible =3D "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names =3D "iface", + "core", + "xo"; + non-removable; + status =3D "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0 0xb000000 0x0 0x1000>, /* GICD */ + <0x0 0xb002000 0x0 0x1000>, /* GICC */ + <0x0 0xb001000 0x0 0x1000>, /* GICH */ + <0x0 0xb004000 0x0 0x1000>; /* GICV */ + interrupts =3D ; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x0b00c000 0 0x3000>; + + v2m0: v2m@0 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x0 0x0 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x00001000 0x0 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x00002000 0x0 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0xb120000 0x0 0x1000>; + ranges =3D <0 0 0 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@b121000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0b123000 0x1000>; + status =3D "disabled"; + }; + + frame@b124000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0b124000 0x1000>; + status =3D "disabled"; + }; + + frame@b125000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0b125000 0x1000>; + status =3D "disabled"; + }; + + frame@b126000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0b126000 0x1000>; + status =3D "disabled"; + }; + + frame@b127000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0b127000 0x1000>; + status =3D "disabled"; + }; + + frame@b128000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x0b128000 0x1000>; + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.34.1