From nobody Tue Apr 7 23:44:31 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B32563BADB3 for ; Wed, 11 Mar 2026 09:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773222378; cv=none; b=ZZHptIc3UfXMAm5yiyONsWUQpnE3KPMl6vMlckH8k1cRKRnxIMPzfXE9BHMMHPdQ/dYLdRjU5CmN6E/bTQbqu3gHyuEOdJbzM4Y+a+/8FV7ZWPgbpxJLqUCw1WMg/FOj6fP6k65evCjp8tlEfKxIvvOrk517UZENYG0PvidqgZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773222378; c=relaxed/simple; bh=RaF0QuXKwHuRbyMdYdDcZ7PSBhm2EjPLewfXNVArYlI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lELD+r50wWmQtV+1K4gHDAqh1dy4/HlIUcQhMy3cHK5LS65YEPqD/Ur5+HLju8svXnHewgAL8RkN6UmEejXqHqKynKcnvUHrIfscgXRYCb4O0d+y+DSq+SexA0sotIDceNR7iCSg3VP7DxgeXs62tK3LMPIM0I31apJgUs75PFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ONPgauk/; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=H6c1dCIA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ONPgauk/"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="H6c1dCIA" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62B4WpAU3417073 for ; Wed, 11 Mar 2026 09:46:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= mtfoC6gmkkEv6OfhHDrmNx1rm9QcUeD7kbqb3pSgfts=; b=ONPgauk/e8Qt387I 8K7EIedrkGmMwp3w8XkU8bVEZDTXddJ3rGNwbQWsMkMNrTlxp5XxqLZ/QeA6Ikkj C4uAy/Ki3V9n2rObtXBM4QumUvvMkN8A6awFrpFpUVkAv12w0Kr0GzpXcrQWpXW+ eFLGDwZg4rKcVvtjCfAQl8+RShvxUg8iR/MLP4+A3RKaA0Ukj2/l3iEHT78q/WK2 Q4rF/dRw7IMw/4J9qNjZ3Vwvah4tMP8Af++sQ/dxBA+zfiTBcSrxtPO7FNhf3cp0 LbdoUE0K/FOqFERCy0IcmUKSp1+hv4FoqzJ2WtnRwcGRSZ/NQ505lmUNz3QzsYEY eCrMKQ== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ctja2ccy2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 09:46:12 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-829a4b6d5c4so2139054b3a.1 for ; Wed, 11 Mar 2026 02:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773222371; x=1773827171; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mtfoC6gmkkEv6OfhHDrmNx1rm9QcUeD7kbqb3pSgfts=; b=H6c1dCIAOKQbPzDS+owATI7CcJrBi+GLgUnwLKrlLMUd4MyIbcD2LdYdlZknROyDj6 jdF1Z1VJssEQhV1CJg0lKcSHlHChS/e9Dr1z5YfK5D7vV3dsbbNehjj9x+FdChvcTZs1 R1Gt1yG8lU6NLjWoox05zOrcVSfIj/NtmsunOZUNraU3e2AwSy8ZE1uMLXWdUFSWqdT/ iWlttdPa3FLN2ZXMhl5wCVQLvjsdC3dJ+Z9/AFca/NxQi0+khaubKEduevxqG4mTjtUq 9UGNZp0py6y6JfwIZkuLm3THcHS50WKAvPd6wKDeAzAB2amo6UwKDBwiToPFgHpEnZuj UCAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773222371; x=1773827171; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mtfoC6gmkkEv6OfhHDrmNx1rm9QcUeD7kbqb3pSgfts=; b=cDEX0lBippYz4zG2WPj/ItXG4UCSB8tocR2vsNp6G0R7tNpLGwLGJ+nDbTFEdgAknj 8Cp8q0El8yRSCLP5U0EXXdwfTbxF6bTpszAJhgatcVDKntNZUXdFPpX0MXCHPoYWgbYF NSB42FyeNxZPKSxMcpOLeNb7f0E+32nMvseVev0dlnnctAeJqRS3JXk3xkDKXrjpQdPO uouN7GUig5xh3jgTT38P7k4K97sV9OUcW2sYvuPeHnRco9ownwUwoLHNX2u+ElaFdP4n xnfXA0Rr3tc9mPng8sRSZJCaepYuku1hie64BPg9KwDvSdNNKVun7s5XPk/PVyX3zj7J ix5A== X-Forwarded-Encrypted: i=1; AJvYcCVoMGT5IkUEnMVZXVqtK0ETHHnrc96qV/1p+HQlhylKowHoapVGkdHbwJBtcPKpLo06EmzwZwNSpF2+6Sk=@vger.kernel.org X-Gm-Message-State: AOJu0YxKTwUsv8w/wg/mjQ1k6sug7fUWXXfqlI3CX5X/V2X8E8t2Mex9 45eDJn6IN9HeBO0TaIeYjpreFbjf5P9bZep8z0N+syg/eiLNxBpGm9WlTuOd8s3lKauN6UUk6cS Weo857vYbl6IwyzG7tvxdJXtEY3QV2Xu/6MhA2BNaqdkawGD/QKSpZzd+MmP8tTY1Y8Y= X-Gm-Gg: ATEYQzyS2wImXry8bdA9jURc0Sg8gEBIWNg3BF0Wbslv88Oqg9d/Xm4WIBW9TuU1Qfl ngTtGpNTPw1TB3kwa2X6P4mY4Wh4+wDtmI8hdbryZCSuvN2ZiWsez5td3XBb+byUxEgejrCI+VE hyfbZWxD6OlIE2ERBE9q/B9tbWTYFNmZX94bbr2sguRjaHwqwptkUAakpbArBjQ8Y5EyFwIbYba lFqyqwATuWINKZeJ7j9WbXW14cwd9BWs+0vAt3PQulI8fc2Uj3RjVMPRgRglWxG4WsycR6/cnyh 37htNo41zyNSPQVzWUemS6Iwwf0VqxjBY+QNO2Zue2IQ4NoIHea8NDeC5qJlIZ5Xq5Y3w3BuaA5 LM9qv1HsoWIRDAX8fxXXBzHPD/T3MOZfbPP+TwdZPWPleLL2V0FPizyAauKmijneIY0KsWJPnak z0l1mekSHYU9kW7AJMDXDlJeyS/YaPkUZNJO4Y4EIpB/c/oDaykM3t2ttD X-Received: by 2002:a05:6a00:a21d:b0:827:298e:b7c0 with SMTP id d2e1a72fcca58-829f7076035mr1931544b3a.47.1773222371284; Wed, 11 Mar 2026 02:46:11 -0700 (PDT) X-Received: by 2002:a05:6a00:a21d:b0:827:298e:b7c0 with SMTP id d2e1a72fcca58-829f7076035mr1931510b3a.47.1773222370772; Wed, 11 Mar 2026 02:46:10 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df5ff0sm1677403b3a.21.2026.03.11.02.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 02:46:10 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 11 Mar 2026 15:15:45 +0530 Subject: [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ipq5210_boot_to_shell-v1-3-fe857d68d698@oss.qualcomm.com> References: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> In-Reply-To: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Linus Walleij , Konrad Dybcio , Ulf Hansson , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mmc@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773222347; l=5789; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=RaF0QuXKwHuRbyMdYdDcZ7PSBhm2EjPLewfXNVArYlI=; b=G+i/GwR3fBoqiog8vNLpSnt9kojpr/LLeiVo1xfhY5r91jb3RCNgOjkA8elGwgdDJJDCqoFlL b1zvtzSAlvYCKRYtBIR0XyNm+SC1oLwTPlljQ+D9fIJzD0njX+PuDd8 X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Authority-Analysis: v=2.4 cv=c9WmgB9l c=1 sm=1 tr=0 ts=69b139e4 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=hD0fcazERHGK-ooIS8AA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: nBA0sR0W4NlhLYoWEk2bluQSJvf1vJ5B X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4MSBTYWx0ZWRfXxtR9AEzGuJSW 8A9buBI9e6ZP5n8j9b0h3RtHEuJz6ITJMEZsDp+dHH4zfswtydbRNCcSsTXDH4y2vpQ3PweB6s7 E+YVxqFXN9iQozY5/x490bbkfSqneruwyYSnKEEW6ncOp+NVian+4XLHcYl1HZlq9LA5VGBfNAY /Bh5diinorq0YpouXWpdxubMhW34DmspuIgg3BjhJAzjpAzAi+PosF7pm4k2qrZY8a9EHyW0KPo 0nX/yxdfLnLWZDt3VC2L1ZtM6v2lnhoLvamkFy4uM3PxrhzI19LsRA00TZjsDILPh2imQN4STlw OBhAvbhn2S9ZOEZcSpcTwsQx4tAd+Sv+fJs3mE3D/fwxwLTcerXiAPMfsLCxnvNHAbjgcPqq4Ad 4OqVlUV5OzGWsqyS1qi5UWG6PB5VsJsIAdeTXgpsWY3WF8RIrAOOWh2pqq/T0rDL4ffqZorU8Pm +ccajGbjBXGRgM1NiFw== X-Proofpoint-GUID: nBA0sR0W4NlhLYoWEk2bluQSJvf1vJ5B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110081 Add device tree bindings for IPQ5210 TLMM block. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.ya= ml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b6= 15c67e642152c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5210 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5210-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5210-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5210-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5210-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, audi= o_pri0, + audio_pri1, audio_pri2, audio_pri3, audio_pri_d0, audio_pr= i_d1, + audio_pri_fsync, audio_pri_pclk, audio_sec0, audio_sec1, + audio_sec2, audio_sec3, audio_sec_d0, audio_sec_d1, + audio_sec_fsync, audio_sec_pclk, core_voltage_0, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, = Led00, + led01, led02, led10, led11, led12, led20, led21, led22, + mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, mdio_slv0, + mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, pcie0_= wake, + pcie1_clk_req_n, pcie1_wake, pll_test, pon_active_led, + pon_mux_sel, pon_rx, pon_rx_los, pon_tx, pon_tx_burst, + pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, gpn_tx_bu= rst, + gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm_out00, pwm_o= ut01, + pwm_out02, pwm_out03, pwm_out10, pwm_out11, pwm_out12, + pwm_out20, pwm_out21, pwm_out22, pwm_out30, pwm_out31, + pwm_out32, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_ou= t_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, + qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2, + qspi_data, qspi_clk, qspi_cs_n, qup_se0_l0, qup_se0_l1, + qup_se0_l2, qup_se0_l3, qup_se0_l4, qup_se0_l5, qup_se1_l0, + qup_se1_l1, qup_se1_l2, qup_se1_l3, qup_se2_l00, qup_se2_l= 01, + qup_se2_l10, qup_se2_l11, qup_se2_l2, qup_se2_l3, qup_se3_= l0, + qup_se3_l1, qup_se3_l2, qup_se3_l3, qup_se4_l0, qup_se4_l1, + qup_se4_l2, qup_se4_l3, qup_se4_l4, qup_se4_l5, qup_se5_l0= 0, + qup_se5_l01, qup_se5_l10, qup_se5_l11, qup_se5_l2, qup_se5= _l3, + qup_se5_l4, qup_se5_l5, resout, rx_los00, rx_los01, rx_los= 10, + rx_los11, rx_los20, rx_los21, sdc_clk, sdc_cmd, sdc_data, + tsens_max ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq5210-tlmm"; + reg =3D <0x01000000 0x300000>; + gpio-controller; + #gpio-cells =3D <0x2>; + gpio-ranges =3D <&tlmm 0 0 54>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <0x2>; + + qup-uart1-default-state { + tx-pins { + pins =3D "gpio39"; + function =3D "qup_se1_l2"; + drive-strength =3D <6>; + bias-pull-down; + }; + + rx-pins { + pins =3D "gpio38"; + function =3D "qup_se1_l3"; + drive-strength =3D <6>; + bias-pull-down; + }; + }; + + }; --=20 2.34.1