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Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,ipq5210-gcc.yaml | 62 ++++++++++ include/dt-bindings/clock/qcom,ipq5210-gcc.h | 126 +++++++++++++++++= +++ include/dt-bindings/reset/qcom,ipq5210-gcc.h | 127 +++++++++++++++++= ++++ 3 files changed, 315 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..aeb5d9a3f8322d5d36d2fd19a1d= 23b275efc34b3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5210 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on IPQ5210 + + See also:: + include/dt-bindings/clock/qcom,ipq5210-gcc.h + include/dt-bindings/reset/qcom,ipq5210-gcc.h + +properties: + compatible: + const: qcom,ipq5210-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: USB3 PHY pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible =3D "qcom,ipq5210-gcc"; + reg =3D <0x01800000 0x40000>; + clocks =3D <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5210-gcc.h b/include/dt-bind= ings/clock/qcom,ipq5210-gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..84116f34ee4d0433a092987e8d1= 89c2aa95da204 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-gcc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_CMN_12GPLL_AHB_CLK 2 +#define GCC_CMN_12GPLL_SYS_CLK 3 +#define GCC_CNOC_LPASS_CFG_CLK 4 +#define GCC_CNOC_PCIE0_1LANE_S_CLK 5 +#define GCC_CNOC_PCIE1_2LANE_S_CLK 6 +#define GCC_CNOC_USB_CLK 7 +#define GCC_GEPHY_SYS_CLK 8 +#define GCC_LPASS_AXIM_CLK_SRC 9 +#define GCC_LPASS_CORE_AXIM_CLK 10 +#define GCC_LPASS_SWAY_CLK 11 +#define GCC_LPASS_SWAY_CLK_SRC 12 +#define GCC_MDIO_AHB_CLK 13 +#define GCC_MDIO_GEPHY_AHB_CLK 14 +#define GCC_NSS_TS_CLK 15 +#define GCC_NSS_TS_CLK_SRC 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_PCIE0_AHB_CLK 31 +#define GCC_PCIE0_AUX_CLK 32 +#define GCC_PCIE0_AXI_M_CLK 33 +#define GCC_PCIE0_AXI_M_CLK_SRC 34 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 +#define GCC_PCIE0_AXI_S_CLK 36 +#define GCC_PCIE0_AXI_S_CLK_SRC 37 +#define GCC_PCIE0_PIPE_CLK 38 +#define GCC_PCIE0_PIPE_CLK_SRC 39 +#define GCC_PCIE0_RCHNG_CLK 40 +#define GCC_PCIE0_RCHNG_CLK_SRC 41 +#define GCC_PCIE1_AHB_CLK 42 +#define GCC_PCIE1_AUX_CLK 43 +#define GCC_PCIE1_AXI_M_CLK 44 +#define GCC_PCIE1_AXI_M_CLK_SRC 45 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 +#define GCC_PCIE1_AXI_S_CLK 47 +#define GCC_PCIE1_AXI_S_CLK_SRC 48 +#define GCC_PCIE1_PIPE_CLK 49 +#define GCC_PCIE1_PIPE_CLK_SRC 50 +#define GCC_PCIE1_RCHNG_CLK 51 +#define GCC_PCIE1_RCHNG_CLK_SRC 52 +#define GCC_PCIE_AUX_CLK_SRC 53 +#define GCC_PCNOC_BFDCD_CLK_SRC 54 +#define GCC_PON_APB_CLK 55 +#define GCC_PON_TM_CLK 56 +#define GCC_PON_TM2X_CLK 57 +#define GCC_PON_TM2X_CLK_SRC 58 +#define GCC_QDSS_AT_CLK 59 +#define GCC_QDSS_AT_CLK_SRC 60 +#define GCC_QDSS_DAP_CLK 61 +#define GCC_QDSS_TSCTR_CLK_SRC 62 +#define GCC_QPIC_AHB_CLK 63 +#define GCC_QPIC_CLK 64 +#define GCC_QPIC_CLK_SRC 65 +#define GCC_QPIC_IO_MACRO_CLK 66 +#define GCC_QPIC_IO_MACRO_CLK_SRC 67 +#define GCC_QRNG_AHB_CLK 68 +#define GCC_QUPV3_AHB_MST_CLK 69 +#define GCC_QUPV3_AHB_SLV_CLK 70 +#define GCC_QUPV3_WRAP_SE0_CLK 71 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 +#define GCC_QUPV3_WRAP_SE1_CLK 73 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 +#define GCC_QUPV3_WRAP_SE2_CLK 75 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 +#define GCC_QUPV3_WRAP_SE3_CLK 77 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 +#define GCC_QUPV3_WRAP_SE4_CLK 79 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 +#define GCC_QUPV3_WRAP_SE5_CLK 81 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 +#define GCC_SDCC1_AHB_CLK 83 +#define GCC_SDCC1_APPS_CLK 84 +#define GCC_SDCC1_APPS_CLK_SRC 85 +#define GCC_SDCC1_ICE_CORE_CLK 86 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 87 +#define GCC_SLEEP_CLK_SRC 88 +#define GCC_SNOC_LPASS_CLK 89 +#define GCC_SNOC_PCIE0_AXI_M_CLK 90 +#define GCC_SNOC_PCIE1_AXI_M_CLK 91 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 +#define GCC_UNIPHY0_AHB_CLK 93 +#define GCC_UNIPHY0_SYS_CLK 94 +#define GCC_UNIPHY1_AHB_CLK 95 +#define GCC_UNIPHY1_SYS_CLK 96 +#define GCC_UNIPHY2_AHB_CLK 97 +#define GCC_UNIPHY2_SYS_CLK 98 +#define GCC_UNIPHY_SYS_CLK_SRC 99 +#define GCC_USB0_AUX_CLK 100 +#define GCC_USB0_AUX_CLK_SRC 101 +#define GCC_USB0_MASTER_CLK 102 +#define GCC_USB0_MASTER_CLK_SRC 103 +#define GCC_USB0_MOCK_UTMI_CLK 104 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 105 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 +#define GCC_USB0_PHY_CFG_AHB_CLK 107 +#define GCC_USB0_PIPE_CLK 108 +#define GCC_USB0_PIPE_CLK_SRC 109 +#define GCC_USB0_SLEEP_CLK 110 +#define GCC_XO_CLK_SRC 111 +#define GPLL0_MAIN 112 +#define GPLL0 113 +#define GPLL2_MAIN 114 +#define GPLL2 115 +#define GPLL4_MAIN 116 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq5210-gcc.h b/include/dt-bind= ings/reset/qcom,ipq5210-gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..09890a09087c39288683d105437= fc68f3d68be4c --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5210-gcc.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3 +#define GCC_APSS_AHB_ARES 4 +#define GCC_APSS_ATB_ARES 5 +#define GCC_APSS_AXI_ARES 6 +#define GCC_APSS_TS_ARES 7 +#define GCC_BOOT_ROM_AHB_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_GEPHY_BCR 10 +#define GCC_GEPHY_SYS_ARES 11 +#define GCC_GP1_ARES 12 +#define GCC_GP2_ARES 13 +#define GCC_GP3_ARES 14 +#define GCC_MDIO_AHB_ARES 15 +#define GCC_MDIO_BCR 16 +#define GCC_MDIO_GEPHY_AHB_ARES 17 +#define GCC_NSS_BCR 18 +#define GCC_NSS_TS_ARES 19 +#define GCC_NSSCC_ARES 20 +#define GCC_NSSCFG_ARES 21 +#define GCC_NSSNOC_ATB_ARES 22 +#define GCC_NSSNOC_MEMNOC_1_ARES 23 +#define GCC_NSSNOC_MEMNOC_ARES 24 +#define GCC_NSSNOC_NSSCC_ARES 25 +#define GCC_NSSNOC_PCNOC_1_ARES 26 +#define GCC_NSSNOC_QOSGEN_REF_ARES 27 +#define GCC_NSSNOC_SNOC_1_ARES 28 +#define GCC_NSSNOC_SNOC_ARES 29 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 30 +#define GCC_NSSNOC_XO_DCD_ARES 31 +#define GCC_PCIE0_AHB_ARES 32 +#define GCC_PCIE0_AUX_ARES 33 +#define GCC_PCIE0_AXI_M_ARES 34 +#define GCC_PCIE0_AXI_S_BRIDGE_ARES 35 +#define GCC_PCIE0_AXI_S_ARES 36 +#define GCC_PCIE0_BCR 37 +#define GCC_PCIE0_LINK_DOWN_BCR 38 +#define GCC_PCIE0_PHY_BCR 39 +#define GCC_PCIE0_PIPE_ARES 40 +#define GCC_PCIE0PHY_PHY_BCR 41 +#define GCC_PCIE1_AHB_ARES 42 +#define GCC_PCIE1_AUX_ARES 43 +#define GCC_PCIE1_AXI_M_ARES 44 +#define GCC_PCIE1_AXI_S_BRIDGE_ARES 45 +#define GCC_PCIE1_AXI_S_ARES 46 +#define GCC_PCIE1_BCR 47 +#define GCC_PCIE1_LINK_DOWN_BCR 48 +#define GCC_PCIE1_PHY_BCR 49 +#define GCC_PCIE1_PIPE_ARES 50 +#define GCC_PCIE1PHY_PHY_BCR 51 +#define GCC_QRNG_AHB_ARES 52 +#define GCC_QRNG_BCR 53 +#define GCC_QUPV3_2X_CORE_ARES 54 +#define GCC_QUPV3_AHB_MST_ARES 55 +#define GCC_QUPV3_AHB_SLV_ARES 56 +#define GCC_QUPV3_BCR 57 +#define GCC_QUPV3_CORE_ARES 58 +#define GCC_QUPV3_WRAP_SE0_ARES 59 +#define GCC_QUPV3_WRAP_SE0_BCR 60 +#define GCC_QUPV3_WRAP_SE1_ARES 61 +#define GCC_QUPV3_WRAP_SE1_BCR 62 +#define GCC_QUPV3_WRAP_SE2_ARES 63 +#define GCC_QUPV3_WRAP_SE2_BCR 64 +#define GCC_QUPV3_WRAP_SE3_ARES 65 +#define GCC_QUPV3_WRAP_SE3_BCR 66 +#define GCC_QUPV3_WRAP_SE4_ARES 67 +#define GCC_QUPV3_WRAP_SE4_BCR 68 +#define GCC_QUPV3_WRAP_SE5_ARES 69 +#define GCC_QUPV3_WRAP_SE5_BCR 70 +#define GCC_QUSB2_0_PHY_BCR 71 +#define GCC_SDCC1_AHB_ARES 72 +#define GCC_SDCC1_APPS_ARES 73 +#define GCC_SDCC1_ICE_CORE_ARES 74 +#define GCC_SDCC_BCR 75 +#define GCC_TLMM_AHB_ARES 76 +#define GCC_TLMM_ARES 77 +#define GCC_TLMM_BCR 78 +#define GCC_UNIPHY0_AHB_ARES 79 +#define GCC_UNIPHY0_BCR 80 +#define GCC_UNIPHY0_SYS_ARES 81 +#define GCC_UNIPHY1_AHB_ARES 82 +#define GCC_UNIPHY1_BCR 83 +#define GCC_UNIPHY1_SYS_ARES 84 +#define GCC_UNIPHY2_AHB_ARES 85 +#define GCC_UNIPHY2_BCR 86 +#define GCC_UNIPHY2_SYS_ARES 87 +#define GCC_USB0_AUX_ARES 88 +#define GCC_USB0_MASTER_ARES 89 +#define GCC_USB0_MOCK_UTMI_ARES 90 +#define GCC_USB0_PHY_BCR 91 +#define GCC_USB0_PHY_CFG_AHB_ARES 92 +#define GCC_USB0_PIPE_ARES 93 +#define GCC_USB0_SLEEP_ARES 94 +#define GCC_USB3PHY_0_PHY_BCR 95 +#define GCC_USB_BCR 96 +#define GCC_PCIE0_PIPE_RESET 97 +#define GCC_PCIE0_CORE_STICKY_RESET 98 +#define GCC_PCIE0_AXI_S_STICKY_RESET 99 +#define GCC_PCIE0_AXI_S_RESET 100 +#define GCC_PCIE0_AXI_M_STICKY_RESET 101 +#define GCC_PCIE0_AXI_M_RESET 102 +#define GCC_PCIE0_AUX_RESET 103 +#define GCC_PCIE0_AHB_RESET 104 +#define GCC_PCIE1_PIPE_RESET 105 +#define GCC_PCIE1_CORE_STICKY_RESET 106 +#define GCC_PCIE1_AXI_S_STICKY_RESET 107 +#define GCC_PCIE1_AXI_S_RESET 108 +#define GCC_PCIE1_AXI_M_STICKY_RESET 109 +#define GCC_PCIE1_AXI_M_RESET 110 +#define GCC_PCIE1_AUX_RESET 111 +#define GCC_PCIE1_AHB_RESET 112 +#define GCC_UNIPHY0_XPCS_ARES 113 +#define GCC_UNIPHY1_XPCS_ARES 114 +#define GCC_UNIPHY2_XPCS_ARES 115 +#define GCC_QDSS_BCR 116 + +#endif --=20 2.34.1 From nobody Tue Apr 7 22:04:33 2026 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df5ff0sm1677403b3a.21.2026.03.11.02.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 02:46:04 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 11 Mar 2026 15:15:44 +0530 Subject: [PATCH 2/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ipq5210_boot_to_shell-v1-2-fe857d68d698@oss.qualcomm.com> References: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> In-Reply-To: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Linus Walleij , Konrad Dybcio , Ulf Hansson , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mmc@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773222347; l=77141; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=k9gCqRY1TJN5tP1zpGefnmeIblIUWKs68PsIzcKsJW0=; b=sddttYw14ncHT3UlH6R+e3vyzoEJiqgwXz1KkkfUsdASJAvNUimjEYTlVPwpaXWWm8T02qP2D hgF2Kngb0WrBZOFg0Y327xvp31WJiRTvacIKKnWCcveO+QlGHKg6/KG X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-GUID: YN9fgcnoRe888xjh4ned8DWuzaWx5fKy X-Proofpoint-ORIG-GUID: YN9fgcnoRe888xjh4ned8DWuzaWx5fKy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4MSBTYWx0ZWRfX94uOG6GmEm+K VvsCz6b86BQPExslP3LFgipBU8ocbh+UepkSXjoR/gFfs9XwhRgkr2+VfN6ZmdvLNUxR6GGvS81 TtohANVMNwpwyis+ZClJAg4gi7YXChzOrSmAsBjwqG3yThUA7TdTFcfbbMv50tb8/RrEp+pCHWi 9TB7OW8D3A7mnzMm9LPGKpxkH6uz3NK+z/bYbBCbPOSea39J/GsEAXt7ndZDoZk1EJxOHnGTl61 X6svSm9UVg5jAjctPBiwGA615lqjGK7cCceZWlScYsX0RCvu20Rp65jAYkwyQMuusDvmOA+UFwJ QgHH3Y75cOvgws4xEy33fYr6IrQYKJYCd2K/brHEyL0x+H5jwr4tInZNUHhYEPNWjOS6pKKGAMp TV6oLOfcWYBTfgm0QmL25eYgVeCh4Xjez37jDXK+V8XHHnjetTwHdU+83VAeWD3FNR7IkJB1UnW ZrLkC/BbhMQkNN5XEWw== X-Authority-Analysis: v=2.4 cv=M4JA6iws c=1 sm=1 tr=0 ts=69b139e0 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=hselGU0lqRRdcXzI58cA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110081 Add support for the global clock controller found on IPQ5210 SoC. Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5210.c | 2641 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 2650 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f23280219d56436fd142a38ff22a219e431539a6..171cb4a6198b1a70a958bc0dfbd= d7b65cdaa7bea 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -332,6 +332,14 @@ config IPQ_GCC_5018 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. =20 +config IPQ_GCC_5210 + tristate "IPQ5210 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + help + Support for the global clock controller on ipq5210 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + i2c, USB, SD/eMMC, etc. + config IPQ_GCC_5332 tristate "IPQ5332 Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 90ea21c3b7cf7956309648c4445ecf8fd61f23b0..c07214c0dd83f43e7847ae37495= 7bf6536cc3451 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o obj-$(CONFIG_IPQ_CMN_PLL) +=3D ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_5018) +=3D gcc-ipq5018.o +obj-$(CONFIG_IPQ_GCC_5210) +=3D gcc-ipq5210.o obj-$(CONFIG_IPQ_GCC_5332) +=3D gcc-ipq5332.o obj-$(CONFIG_IPQ_GCC_5424) +=3D gcc-ipq5424.o obj-$(CONFIG_IPQ_GCC_6018) +=3D gcc-ipq6018.o diff --git a/drivers/clk/qcom/gcc-ipq5210.c b/drivers/clk/qcom/gcc-ipq5210.c new file mode 100644 index 0000000000000000000000000000000000000000..3294a6e116ea984e256e75e9d70= b39a75d685d54 --- /dev/null +++ b/drivers/clk/qcom/gcc-ipq5210.c @@ -0,0 +1,2641 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "reset.h" + +enum { + DT_XO, + DT_SLEEP_CLK, + DT_PCIE30_PHY0_PIPE_CLK, + DT_PCIE30_PHY1_PIPE_CLK, + DT_USB3_PHY0_CC_PIPE_CLK, + DT_NSS_CMN_CLK, +}; + +enum { + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, + P_GPLL0_OUT_AUX, + P_GPLL0_OUT_MAIN, + P_GPLL2_OUT_AUX, + P_GPLL2_OUT_MAIN, + P_GPLL4_OUT_AUX, + P_GPLL4_OUT_MAIN, + P_NSS_CMN_CLK, + P_SLEEP_CLK, + P_USB3PHY_0_PIPE, + P_XO, +}; + +static const struct clk_parent_data gcc_parent_data_xo =3D { .index =3D DT= _XO }; + +static struct clk_alpha_pll gpll0_main =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_div2", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll2_main =3D { + .offset =3D 0x21000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll2[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll2 =3D { + .offset =3D 0x21000, + .post_div_table =3D post_div_table_gpll2, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll2), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll2_main.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll4_main =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + .flags =3D CLK_IS_CRITICAL, + }, + }, +}; +static const struct parent_map gcc_parent_map_xo[] =3D { + { P_XO, 0 }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_XO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_XO }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_XO, 0 }, + { P_NSS_CMN_CLK, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_GPLL2_OUT_AUX, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_NSS_CMN_CLK }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_AUX, 1 }, + { P_GPLL0_OUT_MAIN, 3 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 1 }, + { P_GPLL0_OUT_AUX, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4_main.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_AUX, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_13[] =3D { + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_adss_pwm_clk_src =3D { + .cmd_rcgr =3D 0x1c004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_nss_ts_clk_src =3D { + .cmd_rcgr =3D 0x17088, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x2e004, + .freq_tbl =3D ftbl_gcc_system_noc_bfdcd_clk_src, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_system_noc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] =3D { + F(429000000, P_NSS_CMN_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x17004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] =3D { + F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie0_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x28018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x28020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_rchng_clk_src =3D { + .cmd_rcgr =3D 0x28028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] =3D { + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie1_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x29018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x29020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_rchng_clk_src =3D { + .cmd_rcgr =3D 0x29028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] =3D { + F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + { } +}; + +static struct clk_rcg2 gcc_pcie_aux_clk_src =3D { + .cmd_rcgr =3D 0x28004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_pcie_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] =3D { + F(960000, P_XO, 10, 2, 5), + F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), + F(4800000, P_XO, 5, 0, 0), + F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), + F(9600000, P_XO, 2.5, 0, 0), + F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src =3D { + .cmd_rcgr =3D 0x4004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src =3D { + .cmd_rcgr =3D 0x5004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src =3D { + .cmd_rcgr =3D 0x2018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src =3D { + .cmd_rcgr =3D 0x2034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src =3D { + .cmd_rcgr =3D 0x3018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src =3D { + .cmd_rcgr =3D 0x3034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_XO, 16, 12, 125), + F(400000, P_XO, 12, 1, 5), + F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), + F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), + F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x33004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x33018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static struct clk_rcg2 gcc_uniphy_sys_clk_src =3D { + .cmd_rcgr =3D 0x17090, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy_sys_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb0_aux_clk_src =3D { + .cmd_rcgr =3D 0x2c018, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb0_master_clk_src =3D { + .cmd_rcgr =3D 0x2c004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb0_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] =3D { + F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2), + { } +}; + +static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2c02c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_usb0_mock_utmi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] =3D { + F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_at_clk_src =3D { + .cmd_rcgr =3D 0x2d004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_10, + .freq_tbl =3D ftbl_gcc_qdss_at_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] =3D { + F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_tsctr_clk_src =3D { + .cmd_rcgr =3D 0x2d01c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_10, + .freq_tbl =3D ftbl_gcc_qdss_tsctr_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_tsctr_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x31004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qpic_io_macro_clk_src =3D { + .cmd_rcgr =3D 0x32004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_12, + .freq_tbl =3D ftbl_gcc_qpic_io_macro_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qpic_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qpic_clk_src =3D { + .cmd_rcgr =3D 0x32020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_12, + .freq_tbl =3D ftbl_gcc_qpic_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pon_tm2x_clk_src[] =3D { + F(342860000, P_GPLL4_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pon_tm2x_clk_src =3D { + .cmd_rcgr =3D 0x3c004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_11, + .freq_tbl =3D ftbl_gcc_pon_tm2x_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm2x_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x3400c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_13, + .freq_tbl =3D ftbl_gcc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sleep_clk_src", + .parent_data =3D gcc_parent_data_13, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_13), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] =3D { + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_lpass_sway_clk_src =3D { + .cmd_rcgr =3D 0x27004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_lpass_sway_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_sway_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_lpass_axim_clk_src =3D { + .cmd_rcgr =3D 0x2700c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_lpass_sway_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_axim_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src =3D { + .reg =3D 0x1700c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src =3D { + .reg =3D 0x2c040, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_fixed_factor gcc_pon_tm_div_clk_src =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm_div_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pon_tm2x_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_branch gcc_adss_pwm_clk =3D { + .halt_reg =3D 0x1c00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_adss_pwm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk =3D { + .halt_reg =3D 0x31088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie0_1lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie1_2lane_s_clk =3D { + .halt_reg =3D 0x3108c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie1_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_usb_clk =3D { + .halt_reg =3D 0x310a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x310a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_usb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_ahb_clk =3D { + .halt_reg =3D 0x17040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mdio_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_gephy_ahb_clk =3D { + .halt_reg =3D 0x17098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mdio_gephy_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ts_clk =3D { + .halt_reg =3D 0x17018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nss_ts_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscc_clk =3D { + .halt_reg =3D 0x17034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscfg_clk =3D { + .halt_reg =3D 0x1702c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscfg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_atb_clk =3D { + .halt_reg =3D 0x17014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_1_clk =3D { + .halt_reg =3D 0x17084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_clk =3D { + .halt_reg =3D 0x17024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_nsscc_clk =3D { + .halt_reg =3D 0x17030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 gcc_xo_clk_src =3D { + .cmd_rcgr =3D 0x34004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_xo, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_clk_src", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_xo_div4_clk_src =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_div4_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_branch gcc_gephy_sys_clk =3D { + .halt_reg =3D 0x2a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gephy_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_pcnoc_1_clk =3D { + .halt_reg =3D 0x17080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_pcnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_qosgen_ref_clk =3D { + .halt_reg =3D 0x1701c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_qosgen_ref_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &gcc_xo_div4_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_1_clk =3D { + .halt_reg =3D 0x1707c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1707c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_clk =3D { + .halt_reg =3D 0x17028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_timeout_ref_clk =3D { + .halt_reg =3D 0x17020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_timeout_ref_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_div4_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_xo_dcd_clk =3D { + .halt_reg =3D 0x17074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_xo_dcd_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_ahb_clk =3D { + .halt_reg =3D 0x28030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_aux_clk =3D { + .halt_reg =3D 0x28070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_m_clk =3D { + .halt_reg =3D 0x28038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_bridge_clk =3D { + .halt_reg =3D 0x28048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_clk =3D { + .halt_reg =3D 0x28040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src =3D { + .reg =3D 0x28064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY0_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_pipe_clk =3D { + .halt_reg =3D 0x28068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x28068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_ahb_clk =3D { + .halt_reg =3D 0x29030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_aux_clk =3D { + .halt_reg =3D 0x29074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_m_clk =3D { + .halt_reg =3D 0x29038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_bridge_clk =3D { + .halt_reg =3D 0x29048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_clk =3D { + .halt_reg =3D 0x29040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src =3D { + .reg =3D 0x29064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie1_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY1_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_pipe_clk =3D { + .halt_reg =3D 0x29068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x29068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qrng_ahb_clk =3D { + .halt_reg =3D 0x13024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qrng_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_mst_clk =3D { + .halt_reg =3D 0x1014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_mst_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_slv_clk =3D { + .halt_reg =3D 0x102c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_slv_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se0_clk =3D { + .halt_reg =3D 0x4020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se1_clk =3D { + .halt_reg =3D 0x5020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se2_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se3_clk =3D { + .halt_reg =3D 0x2048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se4_clk =3D { + .halt_reg =3D 0x302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se5_clk =3D { + .halt_reg =3D 0x3048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x3303c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3303c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x3302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x33034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_pcie0_axi_m_clk =3D { + .halt_reg =3D 0x2e04c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_pcie0_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_pcie1_axi_m_clk =3D { + .halt_reg =3D 0x2e050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_pcie1_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_ahb_clk =3D { + .halt_reg =3D 0x1704c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1704c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_sys_clk =3D { + .halt_reg =3D 0x17048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_ahb_clk =3D { + .halt_reg =3D 0x1705c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_sys_clk =3D { + .halt_reg =3D 0x17058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_ahb_clk =3D { + .halt_reg =3D 0x1706c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1706c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_sys_clk =3D { + .halt_reg =3D 0x17068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_aux_clk =3D { + .halt_reg =3D 0x2c04c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_master_clk =3D { + .halt_reg =3D 0x2c044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_mock_utmi_clk =3D { + .halt_reg =3D 0x2c050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x2c05c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_phy_cfg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src =3D { + .reg =3D 0x2c074, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_USB3_PHY0_CC_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_pipe_clk =3D { + .halt_reg =3D 0x2c054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2c054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_usb0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk =3D { + .halt_reg =3D 0x2c058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_rchng_clk =3D { + .halt_reg =3D 0x28028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_rchng_clk =3D { + .halt_reg =3D 0x29028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_ahb_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_clk =3D { + .halt_reg =3D 0x32028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_io_macro_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_io_macro_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_ahb_clk =3D { + .halt_reg =3D 0x3a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_sys_clk =3D { + .halt_reg =3D 0x3a008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_at_clk =3D { + .halt_reg =3D 0x2d034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2d034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk =3D { + .halt_reg =3D 0x2d058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_dap_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pon_apb_clk =3D { + .halt_reg =3D 0x3c01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_apb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pon_tm_clk =3D { + .halt_reg =3D 0x3c014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pon_tm_div_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pon_tm2x_clk =3D { + .halt_reg =3D 0x3c00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pon_tm2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pon_tm2x_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_lpass_clk =3D { + .halt_reg =3D 0x2e028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_lpass_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_axim_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk =3D { + .halt_reg =3D 0x27014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_sway_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_sway_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_lpass_cfg_clk =3D { + .halt_reg =3D 0x31020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_lpass_cfg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_sway_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_core_axim_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_lpass_core_axim_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_lpass_axim_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static __maybe_unused struct clk_regmap *gcc_ipq5210_clocks[] =3D { + [GCC_ADSS_PWM_CLK] =3D &gcc_adss_pwm_clk.clkr, + [GCC_ADSS_PWM_CLK_SRC] =3D &gcc_adss_pwm_clk_src.clkr, + [GCC_CMN_12GPLL_AHB_CLK] =3D &gcc_cmn_12gpll_ahb_clk.clkr, + [GCC_CMN_12GPLL_SYS_CLK] =3D &gcc_cmn_12gpll_sys_clk.clkr, + [GCC_CNOC_LPASS_CFG_CLK] =3D &gcc_cnoc_lpass_cfg_clk.clkr, + [GCC_CNOC_PCIE0_1LANE_S_CLK] =3D &gcc_cnoc_pcie0_1lane_s_clk.clkr, + [GCC_CNOC_PCIE1_2LANE_S_CLK] =3D &gcc_cnoc_pcie1_2lane_s_clk.clkr, + [GCC_CNOC_USB_CLK] =3D &gcc_cnoc_usb_clk.clkr, + [GCC_GEPHY_SYS_CLK] =3D &gcc_gephy_sys_clk.clkr, + [GCC_LPASS_AXIM_CLK_SRC] =3D &gcc_lpass_axim_clk_src.clkr, + [GCC_LPASS_CORE_AXIM_CLK] =3D &gcc_lpass_core_axim_clk.clkr, + [GCC_LPASS_SWAY_CLK] =3D &gcc_lpass_sway_clk.clkr, + [GCC_LPASS_SWAY_CLK_SRC] =3D &gcc_lpass_sway_clk_src.clkr, + [GCC_MDIO_AHB_CLK] =3D &gcc_mdio_ahb_clk.clkr, + [GCC_MDIO_GEPHY_AHB_CLK] =3D &gcc_mdio_gephy_ahb_clk.clkr, + [GCC_NSS_TS_CLK] =3D &gcc_nss_ts_clk.clkr, + [GCC_NSS_TS_CLK_SRC] =3D &gcc_nss_ts_clk_src.clkr, + [GCC_NSSCC_CLK] =3D &gcc_nsscc_clk.clkr, + [GCC_NSSCFG_CLK] =3D &gcc_nsscfg_clk.clkr, + [GCC_NSSNOC_ATB_CLK] =3D &gcc_nssnoc_atb_clk.clkr, + [GCC_NSSNOC_MEMNOC_1_CLK] =3D &gcc_nssnoc_memnoc_1_clk.clkr, + [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] =3D &gcc_nssnoc_memnoc_bfdcd_clk_src.cl= kr, + [GCC_NSSNOC_MEMNOC_CLK] =3D &gcc_nssnoc_memnoc_clk.clkr, + [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] =3D &gcc_nssnoc_memnoc_div_clk_src.clkr, + [GCC_NSSNOC_NSSCC_CLK] =3D &gcc_nssnoc_nsscc_clk.clkr, + [GCC_NSSNOC_PCNOC_1_CLK] =3D &gcc_nssnoc_pcnoc_1_clk.clkr, + [GCC_NSSNOC_QOSGEN_REF_CLK] =3D &gcc_nssnoc_qosgen_ref_clk.clkr, + [GCC_NSSNOC_SNOC_1_CLK] =3D &gcc_nssnoc_snoc_1_clk.clkr, + [GCC_NSSNOC_SNOC_CLK] =3D &gcc_nssnoc_snoc_clk.clkr, + [GCC_NSSNOC_TIMEOUT_REF_CLK] =3D &gcc_nssnoc_timeout_ref_clk.clkr, + [GCC_NSSNOC_XO_DCD_CLK] =3D &gcc_nssnoc_xo_dcd_clk.clkr, + [GCC_PCIE0_AHB_CLK] =3D &gcc_pcie0_ahb_clk.clkr, + [GCC_PCIE0_AUX_CLK] =3D &gcc_pcie0_aux_clk.clkr, + [GCC_PCIE0_AXI_M_CLK] =3D &gcc_pcie0_axi_m_clk.clkr, + [GCC_PCIE0_AXI_M_CLK_SRC] =3D &gcc_pcie0_axi_m_clk_src.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] =3D &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_PCIE0_AXI_S_CLK] =3D &gcc_pcie0_axi_s_clk.clkr, + [GCC_PCIE0_AXI_S_CLK_SRC] =3D &gcc_pcie0_axi_s_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] =3D &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE0_PIPE_CLK_SRC] =3D &gcc_pcie0_pipe_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] =3D &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE0_RCHNG_CLK_SRC] =3D &gcc_pcie0_rchng_clk_src.clkr, + [GCC_PCIE1_AHB_CLK] =3D &gcc_pcie1_ahb_clk.clkr, + [GCC_PCIE1_AUX_CLK] =3D &gcc_pcie1_aux_clk.clkr, + [GCC_PCIE1_AXI_M_CLK] =3D &gcc_pcie1_axi_m_clk.clkr, + [GCC_PCIE1_AXI_M_CLK_SRC] =3D &gcc_pcie1_axi_m_clk_src.clkr, + [GCC_PCIE1_AXI_S_BRIDGE_CLK] =3D &gcc_pcie1_axi_s_bridge_clk.clkr, + [GCC_PCIE1_AXI_S_CLK] =3D &gcc_pcie1_axi_s_clk.clkr, + [GCC_PCIE1_AXI_S_CLK_SRC] =3D &gcc_pcie1_axi_s_clk_src.clkr, + [GCC_PCIE1_PIPE_CLK] =3D &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK_SRC] =3D &gcc_pcie1_pipe_clk_src.clkr, + [GCC_PCIE1_RCHNG_CLK] =3D &gcc_pcie1_rchng_clk.clkr, + [GCC_PCIE1_RCHNG_CLK_SRC] =3D &gcc_pcie1_rchng_clk_src.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCNOC_BFDCD_CLK_SRC] =3D &gcc_pcnoc_bfdcd_clk_src.clkr, + [GCC_PON_APB_CLK] =3D &gcc_pon_apb_clk.clkr, + [GCC_PON_TM_CLK] =3D &gcc_pon_tm_clk.clkr, + [GCC_PON_TM2X_CLK] =3D &gcc_pon_tm2x_clk.clkr, + [GCC_PON_TM2X_CLK_SRC] =3D &gcc_pon_tm2x_clk_src.clkr, + [GCC_QDSS_AT_CLK] =3D &gcc_qdss_at_clk.clkr, + [GCC_QDSS_AT_CLK_SRC] =3D &gcc_qdss_at_clk_src.clkr, + [GCC_QDSS_DAP_CLK] =3D &gcc_qdss_dap_clk.clkr, + [GCC_QDSS_TSCTR_CLK_SRC] =3D &gcc_qdss_tsctr_clk_src.clkr, + [GCC_QPIC_AHB_CLK] =3D &gcc_qpic_ahb_clk.clkr, + [GCC_QPIC_CLK] =3D &gcc_qpic_clk.clkr, + [GCC_QPIC_CLK_SRC] =3D &gcc_qpic_clk_src.clkr, + [GCC_QPIC_IO_MACRO_CLK] =3D &gcc_qpic_io_macro_clk.clkr, + [GCC_QPIC_IO_MACRO_CLK_SRC] =3D &gcc_qpic_io_macro_clk_src.clkr, + [GCC_QRNG_AHB_CLK] =3D &gcc_qrng_ahb_clk.clkr, + [GCC_QUPV3_AHB_MST_CLK] =3D &gcc_qupv3_ahb_mst_clk.clkr, + [GCC_QUPV3_AHB_SLV_CLK] =3D &gcc_qupv3_ahb_slv_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK] =3D &gcc_qupv3_wrap_se0_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK_SRC] =3D &gcc_qupv3_wrap_se0_clk_src.clkr, + [GCC_QUPV3_WRAP_SE1_CLK] =3D &gcc_qupv3_wrap_se1_clk.clkr, + [GCC_QUPV3_WRAP_SE1_CLK_SRC] =3D &gcc_qupv3_wrap_se1_clk_src.clkr, + [GCC_QUPV3_WRAP_SE2_CLK] =3D &gcc_qupv3_wrap_se2_clk.clkr, + [GCC_QUPV3_WRAP_SE2_CLK_SRC] =3D &gcc_qupv3_wrap_se2_clk_src.clkr, + [GCC_QUPV3_WRAP_SE3_CLK] =3D &gcc_qupv3_wrap_se3_clk.clkr, + [GCC_QUPV3_WRAP_SE3_CLK_SRC] =3D &gcc_qupv3_wrap_se3_clk_src.clkr, + [GCC_QUPV3_WRAP_SE4_CLK] =3D &gcc_qupv3_wrap_se4_clk.clkr, + [GCC_QUPV3_WRAP_SE4_CLK_SRC] =3D &gcc_qupv3_wrap_se4_clk_src.clkr, + [GCC_QUPV3_WRAP_SE5_CLK] =3D &gcc_qupv3_wrap_se5_clk.clkr, + [GCC_QUPV3_WRAP_SE5_CLK_SRC] =3D &gcc_qupv3_wrap_se5_clk_src.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SLEEP_CLK_SRC] =3D &gcc_sleep_clk_src.clkr, + [GCC_SNOC_LPASS_CLK] =3D &gcc_snoc_lpass_clk.clkr, + [GCC_SNOC_PCIE0_AXI_M_CLK] =3D &gcc_snoc_pcie0_axi_m_clk.clkr, + [GCC_SNOC_PCIE1_AXI_M_CLK] =3D &gcc_snoc_pcie1_axi_m_clk.clkr, + [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] =3D &gcc_system_noc_bfdcd_clk_src.clkr, + [GCC_UNIPHY0_AHB_CLK] =3D &gcc_uniphy0_ahb_clk.clkr, + [GCC_UNIPHY0_SYS_CLK] =3D &gcc_uniphy0_sys_clk.clkr, + [GCC_UNIPHY1_AHB_CLK] =3D &gcc_uniphy1_ahb_clk.clkr, + [GCC_UNIPHY1_SYS_CLK] =3D &gcc_uniphy1_sys_clk.clkr, + [GCC_UNIPHY2_AHB_CLK] =3D &gcc_uniphy2_ahb_clk.clkr, + [GCC_UNIPHY2_SYS_CLK] =3D &gcc_uniphy2_sys_clk.clkr, + [GCC_UNIPHY_SYS_CLK_SRC] =3D &gcc_uniphy_sys_clk_src.clkr, + [GCC_USB0_AUX_CLK] =3D &gcc_usb0_aux_clk.clkr, + [GCC_USB0_AUX_CLK_SRC] =3D &gcc_usb0_aux_clk_src.clkr, + [GCC_USB0_MASTER_CLK] =3D &gcc_usb0_master_clk.clkr, + [GCC_USB0_MASTER_CLK_SRC] =3D &gcc_usb0_master_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_CLK] =3D &gcc_usb0_mock_utmi_clk.clkr, + [GCC_USB0_MOCK_UTMI_CLK_SRC] =3D &gcc_usb0_mock_utmi_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] =3D &gcc_usb0_mock_utmi_div_clk_src.clkr, + [GCC_USB0_PHY_CFG_AHB_CLK] =3D &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] =3D &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_PIPE_CLK_SRC] =3D &gcc_usb0_pipe_clk_src.clkr, + [GCC_USB0_SLEEP_CLK] =3D &gcc_usb0_sleep_clk.clkr, + [GCC_XO_CLK_SRC] =3D &gcc_xo_clk_src.clkr, + [GPLL0_MAIN] =3D &gpll0_main.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL2_MAIN] =3D &gpll2_main.clkr, + [GPLL2] =3D &gpll2.clkr, + [GPLL4_MAIN] =3D &gpll4_main.clkr, +}; + +static const struct qcom_reset_map gcc_ipq5210_resets[] =3D { + [GCC_ADSS_BCR] =3D { 0x1c000 }, + [GCC_ADSS_PWM_ARES] =3D { 0x1c00c, 2 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] =3D { 0x38000 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES] =3D { 0x3800c, 2 }, + [GCC_APSS_AHB_ARES] =3D { 0x24014, 2 }, + [GCC_APSS_ATB_ARES] =3D { 0x24034, 2 }, + [GCC_APSS_AXI_ARES] =3D { 0x24018, 2 }, + [GCC_APSS_TS_ARES] =3D { 0x24030, 2 }, + [GCC_BOOT_ROM_AHB_ARES] =3D { 0x1302c, 2 }, + [GCC_BOOT_ROM_BCR] =3D { 0x13028 }, + [GCC_GEPHY_BCR] =3D { 0x2a000 }, + [GCC_GEPHY_SYS_ARES] =3D { 0x2a004, 2 }, + [GCC_GP1_ARES] =3D { 0x8018, 2 }, + [GCC_GP2_ARES] =3D { 0x9018, 2 }, + [GCC_GP3_ARES] =3D { 0xa018, 2 }, + [GCC_MDIO_AHB_ARES] =3D { 0x17040, 2 }, + [GCC_MDIO_BCR] =3D { 0x1703c }, + [GCC_MDIO_GEPHY_AHB_ARES] =3D { 0x17098, 2 }, + [GCC_NSS_BCR] =3D { 0x17000 }, + [GCC_NSS_TS_ARES] =3D { 0x17018, 2 }, + [GCC_NSSCC_ARES] =3D { 0x17034, 2 }, + [GCC_NSSCFG_ARES] =3D { 0x1702c, 2 }, + [GCC_NSSNOC_ATB_ARES] =3D { 0x17014, 2 }, + [GCC_NSSNOC_MEMNOC_1_ARES] =3D { 0x17084, 2 }, + [GCC_NSSNOC_MEMNOC_ARES] =3D { 0x17024, 2 }, + [GCC_NSSNOC_NSSCC_ARES] =3D { 0x17030, 2 }, + [GCC_NSSNOC_PCNOC_1_ARES] =3D { 0x17080, 2 }, + [GCC_NSSNOC_QOSGEN_REF_ARES] =3D { 0x1701c, 2 }, + [GCC_NSSNOC_SNOC_1_ARES] =3D { 0x1707c, 2 }, + [GCC_NSSNOC_SNOC_ARES] =3D { 0x17028, 2 }, + [GCC_NSSNOC_TIMEOUT_REF_ARES] =3D { 0x17020, 2 }, + [GCC_NSSNOC_XO_DCD_ARES] =3D { 0x17074, 2 }, + [GCC_PCIE0_AHB_ARES] =3D { 0x28030, 2 }, + [GCC_PCIE0_AUX_ARES] =3D { 0x28070, 2 }, + [GCC_PCIE0_AXI_M_ARES] =3D { 0x28038, 2 }, + [GCC_PCIE0_AXI_S_BRIDGE_ARES] =3D { 0x28048, 2 }, + [GCC_PCIE0_AXI_S_ARES] =3D { 0x28040, 2 }, + [GCC_PCIE0_BCR] =3D { 0x28000 }, + [GCC_PCIE0_LINK_DOWN_BCR] =3D { 0x28054 }, + [GCC_PCIE0_PIPE_RESET] =3D { 0x28058, 0 }, + [GCC_PCIE0_CORE_STICKY_RESET] =3D { 0x28058, 1 }, + [GCC_PCIE0_AXI_S_STICKY_RESET] =3D { 0x28058, 2 }, + [GCC_PCIE0_AXI_S_RESET] =3D { 0x28058, 3 }, + [GCC_PCIE0_AXI_M_STICKY_RESET] =3D { 0x28058, 4 }, + [GCC_PCIE0_AXI_M_RESET] =3D { 0x28058, 5 }, + [GCC_PCIE0_AUX_RESET] =3D { 0x28058, 6 }, + [GCC_PCIE0_AHB_RESET] =3D { 0x28058, 7 }, + [GCC_PCIE0_PHY_BCR] =3D { 0x28060 }, + [GCC_PCIE0_PIPE_ARES] =3D { 0x28068, 2 }, + [GCC_PCIE0PHY_PHY_BCR] =3D { 0x2805c }, + [GCC_PCIE1_AHB_ARES] =3D { 0x29030, 2 }, + [GCC_PCIE1_AUX_ARES] =3D { 0x29074, 2 }, + [GCC_PCIE1_AXI_M_ARES] =3D { 0x29038, 2 }, + [GCC_PCIE1_AXI_S_BRIDGE_ARES] =3D { 0x29048, 2 }, + [GCC_PCIE1_AXI_S_ARES] =3D { 0x29040, 2 }, + [GCC_PCIE1_BCR] =3D { 0x29000 }, + [GCC_PCIE1_LINK_DOWN_BCR] =3D { 0x29054 }, + [GCC_PCIE1_PIPE_RESET] =3D { 0x29058, 0 }, + [GCC_PCIE1_CORE_STICKY_RESET] =3D { 0x29058, 1 }, + [GCC_PCIE1_AXI_S_STICKY_RESET] =3D { 0x29058, 2 }, + [GCC_PCIE1_AXI_S_RESET] =3D { 0x29058, 3 }, + [GCC_PCIE1_AXI_M_STICKY_RESET] =3D { 0x29058, 4 }, + [GCC_PCIE1_AXI_M_RESET] =3D { 0x29058, 5 }, + [GCC_PCIE1_AUX_RESET] =3D { 0x29058, 6 }, + [GCC_PCIE1_AHB_RESET] =3D { 0x29058, 7 }, + [GCC_PCIE1_PHY_BCR] =3D { 0x29060 }, + [GCC_PCIE1_PIPE_ARES] =3D { 0x29068, 2 }, + [GCC_PCIE1PHY_PHY_BCR] =3D { 0x2905c }, + [GCC_QRNG_AHB_ARES] =3D { 0x13024, 2 }, + [GCC_QRNG_BCR] =3D { 0x13020 }, + [GCC_QUPV3_2X_CORE_ARES] =3D { 0x1020, 2 }, + [GCC_QUPV3_AHB_MST_ARES] =3D { 0x1014, 2 }, + [GCC_QUPV3_AHB_SLV_ARES] =3D { 0x102c, 2 }, + [GCC_QUPV3_BCR] =3D { 0x1000 }, + [GCC_QUPV3_CORE_ARES] =3D { 0x1018, 2 }, + [GCC_QUPV3_WRAP_SE0_ARES] =3D { 0x4020, 2 }, + [GCC_QUPV3_WRAP_SE0_BCR] =3D { 0x4000 }, + [GCC_QUPV3_WRAP_SE1_ARES] =3D { 0x5020, 2 }, + [GCC_QUPV3_WRAP_SE1_BCR] =3D { 0x5000 }, + [GCC_QUPV3_WRAP_SE2_ARES] =3D { 0x202c, 2 }, + [GCC_QUPV3_WRAP_SE2_BCR] =3D { 0x2000 }, + [GCC_QUPV3_WRAP_SE3_ARES] =3D { 0x2048, 2 }, + [GCC_QUPV3_WRAP_SE3_BCR] =3D { 0x2030 }, + [GCC_QUPV3_WRAP_SE4_ARES] =3D { 0x302c, 2 }, + [GCC_QUPV3_WRAP_SE4_BCR] =3D { 0x3000 }, + [GCC_QUPV3_WRAP_SE5_ARES] =3D { 0x3048, 2 }, + [GCC_QUPV3_WRAP_SE5_BCR] =3D { 0x3030 }, + [GCC_QUSB2_0_PHY_BCR] =3D { 0x2c068 }, + [GCC_SDCC1_AHB_ARES] =3D { 0x3303c, 2 }, + [GCC_SDCC1_APPS_ARES] =3D { 0x3302c, 2 }, + [GCC_SDCC1_ICE_CORE_ARES] =3D { 0x33034, 2 }, + [GCC_SDCC_BCR] =3D { 0x33000 }, + [GCC_TLMM_AHB_ARES] =3D { 0x3e004, 2 }, + [GCC_TLMM_ARES] =3D { 0x3e008, 2 }, + [GCC_TLMM_BCR] =3D { 0x3e000 }, + [GCC_UNIPHY0_AHB_ARES] =3D { 0x1704c, 2 }, + [GCC_UNIPHY0_BCR] =3D { 0x17044 }, + [GCC_UNIPHY0_SYS_ARES] =3D { 0x17048, 2 }, + [GCC_UNIPHY1_AHB_ARES] =3D { 0x1705c, 2 }, + [GCC_UNIPHY1_BCR] =3D { 0x17054 }, + [GCC_UNIPHY1_SYS_ARES] =3D { 0x17058, 2 }, + [GCC_UNIPHY2_AHB_ARES] =3D { 0x1706c, 2 }, + [GCC_UNIPHY2_BCR] =3D { 0x17064 }, + [GCC_UNIPHY2_SYS_ARES] =3D { 0x17068, 2 }, + [GCC_USB0_AUX_ARES] =3D { 0x2c04c, 2 }, + [GCC_USB0_MASTER_ARES] =3D { 0x2c044, 2 }, + [GCC_USB0_MOCK_UTMI_ARES] =3D { 0x2c050, 2 }, + [GCC_USB0_PHY_BCR] =3D { 0x2c06c }, + [GCC_USB0_PHY_CFG_AHB_ARES] =3D { 0x2c05c, 2 }, + [GCC_USB0_PIPE_ARES] =3D { 0x2c054, 2 }, + [GCC_USB0_SLEEP_ARES] =3D { 0x2c058, 2 }, + [GCC_USB3PHY_0_PHY_BCR] =3D { 0x2c070 }, + [GCC_USB_BCR] =3D { 0x2c000 }, + [GCC_QDSS_BCR] =3D { 0x2d000 }, +}; + +static const struct of_device_id gcc_ipq5210_match_table[] =3D { + { .compatible =3D "qcom,ipq5210-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_ipq5210_match_table); + +static const struct regmap_config gcc_ipq5210_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3f024, + .fast_io =3D true, +}; + +static struct clk_hw *gcc_ipq5210_hws[] =3D { + &gpll0_div2.hw, + &gcc_xo_div4_clk_src.hw, + &gcc_pon_tm_div_clk_src.hw, +}; + +static const struct qcom_cc_desc gcc_ipq5210_desc =3D { + .config =3D &gcc_ipq5210_regmap_config, + .clks =3D gcc_ipq5210_clocks, + .num_clks =3D ARRAY_SIZE(gcc_ipq5210_clocks), + .resets =3D gcc_ipq5210_resets, + .num_resets =3D ARRAY_SIZE(gcc_ipq5210_resets), + .clk_hws =3D gcc_ipq5210_hws, + .num_clk_hws =3D ARRAY_SIZE(gcc_ipq5210_hws), +}; + +static int gcc_ipq5210_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_ipq5210_desc); +} + +static struct platform_driver gcc_ipq5210_driver =3D { + .probe =3D gcc_ipq5210_probe, + .driver =3D { + .name =3D "qcom,gcc-ipq5210", + .of_match_table =3D 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df5ff0sm1677403b3a.21.2026.03.11.02.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 02:46:10 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 11 Mar 2026 15:15:45 +0530 Subject: [PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ipq5210_boot_to_shell-v1-3-fe857d68d698@oss.qualcomm.com> References: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> In-Reply-To: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Linus Walleij , Konrad Dybcio , Ulf Hansson , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mmc@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773222347; l=5789; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=RaF0QuXKwHuRbyMdYdDcZ7PSBhm2EjPLewfXNVArYlI=; b=G+i/GwR3fBoqiog8vNLpSnt9kojpr/LLeiVo1xfhY5r91jb3RCNgOjkA8elGwgdDJJDCqoFlL b1zvtzSAlvYCKRYtBIR0XyNm+SC1oLwTPlljQ+D9fIJzD0njX+PuDd8 X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Authority-Analysis: v=2.4 cv=c9WmgB9l c=1 sm=1 tr=0 ts=69b139e4 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=hD0fcazERHGK-ooIS8AA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: nBA0sR0W4NlhLYoWEk2bluQSJvf1vJ5B X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4MSBTYWx0ZWRfXxtR9AEzGuJSW 8A9buBI9e6ZP5n8j9b0h3RtHEuJz6ITJMEZsDp+dHH4zfswtydbRNCcSsTXDH4y2vpQ3PweB6s7 E+YVxqFXN9iQozY5/x490bbkfSqneruwyYSnKEEW6ncOp+NVian+4XLHcYl1HZlq9LA5VGBfNAY /Bh5diinorq0YpouXWpdxubMhW34DmspuIgg3BjhJAzjpAzAi+PosF7pm4k2qrZY8a9EHyW0KPo 0nX/yxdfLnLWZDt3VC2L1ZtM6v2lnhoLvamkFy4uM3PxrhzI19LsRA00TZjsDILPh2imQN4STlw OBhAvbhn2S9ZOEZcSpcTwsQx4tAd+Sv+fJs3mE3D/fwxwLTcerXiAPMfsLCxnvNHAbjgcPqq4Ad 4OqVlUV5OzGWsqyS1qi5UWG6PB5VsJsIAdeTXgpsWY3WF8RIrAOOWh2pqq/T0rDL4ffqZorU8Pm +ccajGbjBXGRgM1NiFw== X-Proofpoint-GUID: nBA0sR0W4NlhLYoWEk2bluQSJvf1vJ5B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110081 Add device tree bindings for IPQ5210 TLMM block. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.ya= ml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b6= 15c67e642152c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5210 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5210-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5210-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5210-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5210-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, audi= o_pri0, + audio_pri1, audio_pri2, audio_pri3, audio_pri_d0, audio_pr= i_d1, + audio_pri_fsync, audio_pri_pclk, audio_sec0, audio_sec1, + audio_sec2, audio_sec3, audio_sec_d0, audio_sec_d1, + audio_sec_fsync, audio_sec_pclk, core_voltage_0, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, = Led00, + led01, led02, led10, led11, led12, led20, led21, led22, + mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, mdio_slv0, + mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, pcie0_= wake, + pcie1_clk_req_n, pcie1_wake, pll_test, pon_active_led, + pon_mux_sel, pon_rx, pon_rx_los, pon_tx, pon_tx_burst, + pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, gpn_tx_bu= rst, + gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm_out00, pwm_o= ut01, + pwm_out02, pwm_out03, pwm_out10, pwm_out11, pwm_out12, + pwm_out20, pwm_out21, pwm_out22, pwm_out30, pwm_out31, + pwm_out32, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_ou= t_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, + qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2, + qspi_data, qspi_clk, qspi_cs_n, qup_se0_l0, qup_se0_l1, + qup_se0_l2, qup_se0_l3, qup_se0_l4, qup_se0_l5, qup_se1_l0, + qup_se1_l1, qup_se1_l2, qup_se1_l3, qup_se2_l00, qup_se2_l= 01, + qup_se2_l10, qup_se2_l11, qup_se2_l2, qup_se2_l3, qup_se3_= l0, + qup_se3_l1, qup_se3_l2, qup_se3_l3, qup_se4_l0, qup_se4_l1, + qup_se4_l2, qup_se4_l3, qup_se4_l4, qup_se4_l5, qup_se5_l0= 0, + qup_se5_l01, qup_se5_l10, qup_se5_l11, qup_se5_l2, qup_se5= _l3, + qup_se5_l4, qup_se5_l5, resout, rx_los00, rx_los01, rx_los= 10, + rx_los11, rx_los20, rx_los21, sdc_clk, sdc_cmd, sdc_data, + tsens_max ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq5210-tlmm"; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df5ff0sm1677403b3a.21.2026.03.11.02.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 02:46:16 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 11 Mar 2026 15:15:46 +0530 Subject: [PATCH 4/9] pinctrl: qcom: Introduce IPQ5210 TLMM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ipq5210_boot_to_shell-v1-4-fe857d68d698@oss.qualcomm.com> References: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> In-Reply-To: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Linus Walleij , Konrad Dybcio , Ulf Hansson , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mmc@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773222347; l=33467; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=RNXZrAiQpfM/1qCkfKjcDQHfT/ssVSBDe3QuiZjsQqQ=; b=d5wLXAVVCY7KgvbkKci2+9pL69bg9n0QhnfbcQEvk/IWciQX6NpwkXAE8D9/NqIme3WGCzgxX 2u2V1cdfNiwBB4fq8V1K6jGkHhMrsnsFyw3eS6JD3XhmYe07VIA8vG3 X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4MSBTYWx0ZWRfX0eue1OFoZOEh crrdx0yVcBjHDt9z4PkI+cRDWC3y7rO+Ly3NNYPbFwvQcyJPrF8MlczRoldSj9Bo+hB7fdsbZ9s unaQJ3JQypzzTiL26mrS7qs6C97R0LvuTZc3qWVhjv2XWXs1IBm8DNBAOWQLKVqpVBWD2mpq7Pa GYlAhxLciNErfm7IkfvYAtE+5Xxa1Owh0gNyaOfMspMCjX4eKGoW1bgsf4jaY395ORk+qmpiZF5 v+Km+3/8OfBmnUQrSzC4ws7kFQatQ1LYKhqcbaEl8qXfIZ6m0beq5YHt8lBsNvJQCmeQQFjMDQy jP5OtdNQ7JhTXKAj5q6fi8uIdjTx/0uHSUxquhlleSFTU4iiemswyeASponjVe7W96IDDYw/ZFm jPypj+6Vwp2X3Gtvw2FFt86UjeeVzlnuUfiO+1zACV9fKIC36k7bbWQYSxq0vrTHIL7paI0tnvO u7HuVYyZ5tqRLXNH0yA== X-Proofpoint-GUID: 9PRZS7e0A-Jo7y6BpmtzNYKnLuCwBfH6 X-Proofpoint-ORIG-GUID: 9PRZS7e0A-Jo7y6BpmtzNYKnLuCwBfH6 X-Authority-Analysis: v=2.4 cv=Cq+ys34D c=1 sm=1 tr=0 ts=69b139ea cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=4Iti9FFGXJfufOaZZOAA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110081 Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms, so add a driver for it. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5210.c | 1156 ++++++++++++++++++++++++++++= ++++ 3 files changed, 1165 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 6df6159fa5f89f9f0470e700b4698dc8849ed515..17416dce8e70cce022c6ffdc2d3= ac8adf7aae1ff 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -58,6 +58,14 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. =20 +config PINCTRL_IPQ5210 + tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc IPQ5210 platform. + config PINCTRL_IPQ5332 tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a8fd12f90d6e6f8e139097cc0a81d6f178f09000..84ff95ff246a4073508d60e92a0= 9f82f989bb50f 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_GLYMUR) +=3D pinctrl-glymur.o obj-$(CONFIG_PINCTRL_IPQ4019) +=3D pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) +=3D pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) +=3D pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ5210) +=3D pinctrl-ipq5210.o obj-$(CONFIG_PINCTRL_IPQ5332) +=3D pinctrl-ipq5332.o obj-$(CONFIG_PINCTRL_IPQ5424) +=3D pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) +=3D pinctrl-ipq8074.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5210.c b/drivers/pinctrl/qcom/= pinctrl-ipq5210.c new file mode 100644 index 0000000000000000000000000000000000000000..182bfeae6b30f79ed289cbe3c2d= 6ba8bb28705f8 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5210.c @@ -0,0 +1,1156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg =3D REG_SIZE * id, \ + .io_reg =3D 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D 0xc + REG_SIZE * id, \ + .intr_target_reg =3D 0x8 + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs =3D 10, \ + } + +static const struct pinctrl_pin_desc ipq5210_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); + +enum ipq5210_functions { + msm_mux_atest_char_start, + msm_mux_atest_char_status0, + msm_mux_atest_char_status1, + msm_mux_atest_char_status2, + msm_mux_atest_char_status3, + msm_mux_atest_tic_en, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_pri2, + msm_mux_audio_pri3, + msm_mux_audio_pri_d0, + msm_mux_audio_pri_d1, + msm_mux_audio_pri_fsync, + msm_mux_audio_pri_pclk, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_audio_sec2, + msm_mux_audio_sec3, + msm_mux_audio_sec_d0, + msm_mux_audio_sec_d1, + msm_mux_audio_sec_fsync, + msm_mux_audio_sec_pclk, + msm_mux_core_voltage_0, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_dbg_out_clk, + msm_mux_dg_out, + msm_mux_gcc_plltest_bypassnl, + msm_mux_gcc_plltest_resetn, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_Led00, + msm_mux_led01, + msm_mux_led02, + msm_mux_led10, + msm_mux_led11, + msm_mux_led12, + msm_mux_led20, + msm_mux_led21, + msm_mux_led22, + msm_mux_mdc_mst, + msm_mux_mdc_slv0, + msm_mux_mdc_slv1, + msm_mux_mdc_slv2, + msm_mux_mdio_mst, + msm_mux_mdio_slv0, + msm_mux_mdio_slv1, + msm_mux_mdio_slv2, + msm_mux_mux_tod_out, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_wake, + msm_mux_pll_test, + msm_mux_pon_active_led, + msm_mux_pon_mux_sel, + msm_mux_pon_rx, + msm_mux_pon_rx_los, + msm_mux_pon_tx, + msm_mux_pon_tx_burst, + msm_mux_pon_tx_dis, + msm_mux_pon_tx_fault, + msm_mux_pon_tx_sd, + msm_mux_gpn_rx_los, + msm_mux_gpn_tx_burst, + msm_mux_gpn_tx_dis, + msm_mux_gpn_tx_fault, + msm_mux_gpn_tx_sd, + msm_mux_pps, + msm_mux_pwm_out00, + msm_mux_pwm_out01, + msm_mux_pwm_out02, + msm_mux_pwm_out03, + msm_mux_pwm_out10, + msm_mux_pwm_out11, + msm_mux_pwm_out12, + msm_mux_pwm_out20, + msm_mux_pwm_out21, + msm_mux_pwm_out22, + msm_mux_pwm_out30, + msm_mux_pwm_out31, + msm_mux_pwm_out32, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qrng_rosc0, + msm_mux_qrng_rosc1, + msm_mux_qrng_rosc2, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs_n, + msm_mux_qup_se0_l0, + msm_mux_qup_se0_l1, + msm_mux_qup_se0_l2, + msm_mux_qup_se0_l3, + msm_mux_qup_se0_l4, + msm_mux_qup_se0_l5, + msm_mux_qup_se1_l0, + msm_mux_qup_se1_l1, + msm_mux_qup_se1_l2, + msm_mux_qup_se1_l3, + msm_mux_qup_se2_l00, + msm_mux_qup_se2_l01, + msm_mux_qup_se2_l10, + msm_mux_qup_se2_l11, + msm_mux_qup_se2_l2, + msm_mux_qup_se2_l3, + msm_mux_qup_se3_l0, + msm_mux_qup_se3_l1, + msm_mux_qup_se3_l2, + msm_mux_qup_se3_l3, + msm_mux_qup_se4_l0, + msm_mux_qup_se4_l1, + msm_mux_qup_se4_l2, + msm_mux_qup_se4_l3, + msm_mux_qup_se4_l4, + msm_mux_qup_se4_l5, + msm_mux_qup_se5_l00, + msm_mux_qup_se5_l01, + msm_mux_qup_se5_l10, + msm_mux_qup_se5_l11, + msm_mux_qup_se5_l2, + msm_mux_qup_se5_l3, + msm_mux_qup_se5_l4, + msm_mux_qup_se5_l5, + msm_mux_resout, + msm_mux_rx_los00, + msm_mux_rx_los01, + msm_mux_rx_los10, + msm_mux_rx_los11, + msm_mux_rx_los20, + msm_mux_rx_los21, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_tsens_max, + msm_mux__, +}; + +static const char *const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char *const atest_char_start_groups[] =3D { + "gpio46", +}; + +static const char *const atest_char_status0_groups[] =3D { + "gpio34", +}; + +static const char *const atest_char_status1_groups[] =3D { + "gpio35", +}; + +static const char *const atest_char_status2_groups[] =3D { + "gpio36", +}; + +static const char *const atest_char_status3_groups[] =3D { + "gpio37", +}; + +static const char *const atest_tic_en_groups[] =3D { + "gpio42", +}; + +static const char *const audio_pri0_groups[] =3D { + "gpio12", +}; + +static const char *const audio_pri1_groups[] =3D { + "gpio19", +}; + +static const char *const audio_pri2_groups[] =3D { + "gpio8", +}; + +static const char *const audio_pri3_groups[] =3D { + "gpio13", +}; + +static const char *const audio_pri_d0_groups[] =3D { + "gpio34", +}; + +static const char *const audio_pri_d1_groups[] =3D { + "gpio35", +}; + +static const char *const audio_pri_fsync_groups[] =3D { + "gpio36", +}; + +static const char *const audio_pri_pclk_groups[] =3D { + "gpio37", +}; + +static const char *const audio_sec0_groups[] =3D { + "gpio17", +}; + +static const char *const audio_sec1_groups[] =3D { + "gpio16", +}; + +static const char *const audio_sec2_groups[] =3D { + "gpio49", +}; + +static const char *const audio_sec3_groups[] =3D { + "gpio50", +}; + +static const char *const audio_sec_d0_groups[] =3D { + "gpio43", +}; + +static const char *const audio_sec_d1_groups[] =3D { + "gpio42", +}; + +static const char *const audio_sec_fsync_groups[] =3D { + "gpio40", +}; + +static const char *const audio_sec_pclk_groups[] =3D { + "gpio41", +}; + +static const char *const core_voltage_0_groups[] =3D { + "gpio22", +}; + +static const char *const cri_trng0_groups[] =3D { + "gpio6", +}; + +static const char *const cri_trng1_groups[] =3D { + "gpio7", +}; + +static const char *const cri_trng2_groups[] =3D { + "gpio8", +}; + +static const char *const cri_trng3_groups[] =3D { + "gpio9", +}; + +static const char *const dbg_out_clk_groups[] =3D { + "gpio23", +}; + +static const char *const dg_out_groups[] =3D { + "gpio46", +}; + +static const char *const gcc_plltest_bypassnl_groups[] =3D { + "gpio38", +}; + +static const char *const gcc_plltest_resetn_groups[] =3D { + "gpio40", +}; + +static const char *const gcc_tlmm_groups[] =3D { + "gpio39", +}; + +static const char *const Led00_groups[] =3D { + "gpio23", +}; + +static const char *const led01_groups[] =3D { + "gpio39", +}; + +static const char *const led02_groups[] =3D { + "gpio6", +}; + +static const char *const led10_groups[] =3D { + "gpio39", +}; + +static const char *const led11_groups[] =3D { + "gpio27", +}; + +static const char *const led12_groups[] =3D { + "gpio7", +}; + +static const char *const led20_groups[] =3D { + "gpio38", +}; + +static const char *const led21_groups[] =3D { + "gpio26", +}; + +static const char *const led22_groups[] =3D { + "gpio9", +}; + +static const char *const mdc_mst_groups[] =3D { + "gpio26", +}; + +static const char *const mdc_slv0_groups[] =3D { + "gpio31", +}; + +static const char *const mdc_slv1_groups[] =3D { + "gpio20", +}; + +static const char *const mdc_slv2_groups[] =3D { + "gpio47", +}; + +static const char *const mdio_mst_groups[] =3D { + "gpio27", +}; + +static const char *const mdio_slv0_groups[] =3D { + "gpio33", +}; + +static const char *const mdio_slv1_groups[] =3D { + "gpio21", +}; + +static const char *const mdio_slv2_groups[] =3D { + "gpio49", +}; + +static const char *const mux_tod_out_groups[] =3D { + "gpio19", +}; + +static const char *const pcie0_clk_req_n_groups[] =3D { + "gpio31", +}; + +static const char *const pcie0_wake_groups[] =3D { + "gpio33", +}; + +static const char *const pcie1_clk_req_n_groups[] =3D { + "gpio28", +}; + +static const char *const pcie1_wake_groups[] =3D { + "gpio30", +}; + +static const char *const pll_test_groups[] =3D { + "gpio18", +}; + +static const char *const pon_active_led_groups[] =3D { + "gpio11", +}; + +static const char *const pon_mux_sel_groups[] =3D { + "gpio45", +}; + +static const char *const pon_rx_groups[] =3D { + "gpio48", +}; + +static const char *const pon_rx_los_groups[] =3D { + "gpio10", +}; + +static const char *const pon_tx_groups[] =3D { + "gpio15", +}; + +static const char *const pon_tx_burst_groups[] =3D { + "gpio14", +}; + +static const char *const pon_tx_dis_groups[] =3D { + "gpio12", +}; + +static const char *const pon_tx_fault_groups[] =3D { + "gpio17", +}; + +static const char *const pon_tx_sd_groups[] =3D { + "gpio16", +}; + +static const char *const gpn_rx_los_groups[] =3D { + "gpio47", +}; + +static const char *const gpn_tx_burst_groups[] =3D { + "gpio51", +}; + +static const char *const gpn_tx_dis_groups[] =3D { + "gpio13", +}; + +static const char *const gpn_tx_fault_groups[] =3D { + "gpio49", +}; + +static const char *const gpn_tx_sd_groups[] =3D { + "gpio50", +}; + +static const char *const pps_groups[] =3D { + "gpio18", +}; + +static const char *const pwm_out00_groups[] =3D { + "gpio13", +}; + +static const char *const pwm_out01_groups[] =3D { + "gpio9", +}; + +static const char *const pwm_out02_groups[] =3D { + "gpio3", +}; + +static const char *const pwm_out03_groups[] =3D { + "gpio22", +}; + +static const char *const pwm_out10_groups[] =3D { + "gpio12", +}; + +static const char *const pwm_out11_groups[] =3D { + "gpio8", +}; + +static const char *const pwm_out12_groups[] =3D { + "gpio2", +}; + +static const char *const pwm_out20_groups[] =3D { + "gpio11", +}; + +static const char *const pwm_out21_groups[] =3D { + "gpio7", +}; + +static const char *const pwm_out22_groups[] =3D { + "gpio1", +}; + +static const char *const pwm_out30_groups[] =3D { + "gpio10", +}; + +static const char *const pwm_out31_groups[] =3D { + "gpio6", +}; + +static const char *const pwm_out32_groups[] =3D { + "gpio0", +}; + +static const char *const qdss_cti_trig_in_a0_groups[] =3D { + "gpio30", +}; + +static const char *const qdss_cti_trig_in_a1_groups[] =3D { + "gpio33", +}; + +static const char *const qdss_cti_trig_in_b0_groups[] =3D { + "gpio34", +}; + +static const char *const qdss_cti_trig_in_b1_groups[] =3D { + "gpio37", +}; + +static const char *const qdss_cti_trig_out_a0_groups[] =3D { + "gpio28", +}; + +static const char *const qdss_cti_trig_out_a1_groups[] =3D { + "gpio31", +}; + +static const char *const qdss_cti_trig_out_b0_groups[] =3D { + "gpio16", +}; + +static const char *const qdss_cti_trig_out_b1_groups[] =3D { + "gpio35", +}; + +static const char *const qdss_traceclk_a_groups[] =3D { + "gpio23", +}; + +static const char *const qdss_tracectl_a_groups[] =3D { + "gpio26", +}; + +static const char *const qdss_tracedata_a_groups[] =3D { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char *const qrng_rosc0_groups[] =3D { + "gpio12", +}; + +static const char *const qrng_rosc1_groups[] =3D { + "gpio13", +}; + +static const char *const qrng_rosc2_groups[] =3D { + "gpio14", +}; + +static const char *const qspi_data_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qspi_clk_groups[] =3D { + "gpio5", +}; + +static const char *const qspi_cs_n_groups[] =3D { + "gpio4", +}; + +static const char *const qup_se0_l0_groups[] =3D { + "gpio8", +}; + +static const char *const qup_se0_l1_groups[] =3D { + "gpio9", +}; + +static const char *const qup_se0_l2_groups[] =3D { + "gpio6", +}; + +static const char *const qup_se0_l3_groups[] =3D { + "gpio7", +}; + +static const char *const qup_se0_l4_groups[] =3D { + "gpio14", +}; + +static const char *const qup_se0_l5_groups[] =3D { + "gpio15", +}; + +static const char *const qup_se1_l0_groups[] =3D { + "gpio30", +}; + +static const char *const qup_se1_l1_groups[] =3D { + "gpio28", +}; + +static const char *const qup_se1_l2_groups[] =3D { + "gpio39", +}; + +static const char *const qup_se1_l3_groups[] =3D { + "gpio38", +}; + +static const char *const qup_se2_l00_groups[] =3D { + "gpio21", +}; + +static const char *const qup_se2_l01_groups[] =3D { + "gpio53", +}; + +static const char *const qup_se2_l10_groups[] =3D { + "gpio20", +}; + +static const char *const qup_se2_l11_groups[] =3D { + "gpio52", +}; + +static const char *const qup_se2_l2_groups[] =3D { + "gpio13", +}; + +static const char *const qup_se2_l3_groups[] =3D { + "gpio12", +}; + +static const char *const qup_se3_l0_groups[] =3D { + "gpio23", +}; + +static const char *const qup_se3_l1_groups[] =3D { + "gpio22", +}; + +static const char *const qup_se3_l2_groups[] =3D { + "gpio11", +}; + +static const char *const qup_se3_l3_groups[] =3D { + "gpio10", +}; + +static const char *const qup_se4_l0_groups[] =3D { + "gpio42", +}; + +static const char *const qup_se4_l1_groups[] =3D { + "gpio43", +}; + +static const char *const qup_se4_l2_groups[] =3D { + "gpio40", +}; + +static const char *const qup_se4_l3_groups[] =3D { + "gpio41", +}; + +static const char *const qup_se4_l4_groups[] =3D { + "gpio52", +}; + +static const char *const qup_se4_l5_groups[] =3D { + "gpio53", +}; + +static const char *const qup_se5_l00_groups[] =3D { + "gpio49", +}; + +static const char *const qup_se5_l01_groups[] =3D { + "gpio52", +}; + +static const char *const qup_se5_l10_groups[] =3D { + "gpio50", +}; + +static const char *const qup_se5_l11_groups[] =3D { + "gpio53", +}; + +static const char *const qup_se5_l2_groups[] =3D { + "gpio47", +}; + +static const char *const qup_se5_l3_groups[] =3D { + "gpio48", +}; + +static const char *const qup_se5_l4_groups[] =3D { + "gpio51", +}; + +static const char *const qup_se5_l5_groups[] =3D { + "gpio52", +}; + +static const char *const resout_groups[] =3D { + "gpio44", +}; + +static const char *const rx_los00_groups[] =3D { + "gpio42", +}; + +static const char *const rx_los01_groups[] =3D { + "gpio37", +}; + +static const char *const rx_los10_groups[] =3D { + "gpio41", +}; + +static const char *const rx_los11_groups[] =3D { + "gpio36", +}; + +static const char *const rx_los20_groups[] =3D { + "gpio40", +}; + +static const char *const rx_los21_groups[] =3D { + "gpio35", +}; + +static const char *const sdc_clk_groups[] =3D { + "gpio5", +}; + +static const char *const sdc_cmd_groups[] =3D { + "gpio4", +}; + +static const char *const sdc_data_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const tsens_max_groups[] =3D { + "gpio20", +}; + +static const struct pinfunction ipq5210_functions[] =3D { + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_char_status0), + MSM_PIN_FUNCTION(atest_char_status1), + MSM_PIN_FUNCTION(atest_char_status2), + MSM_PIN_FUNCTION(atest_char_status3), + MSM_PIN_FUNCTION(atest_tic_en), + MSM_PIN_FUNCTION(audio_pri0), + MSM_PIN_FUNCTION(audio_pri1), + MSM_PIN_FUNCTION(audio_pri2), + MSM_PIN_FUNCTION(audio_pri3), + MSM_PIN_FUNCTION(audio_pri_d0), + MSM_PIN_FUNCTION(audio_pri_d1), + MSM_PIN_FUNCTION(audio_pri_fsync), + MSM_PIN_FUNCTION(audio_pri_pclk), + MSM_PIN_FUNCTION(audio_sec0), + MSM_PIN_FUNCTION(audio_sec1), + MSM_PIN_FUNCTION(audio_sec2), + MSM_PIN_FUNCTION(audio_sec3), + MSM_PIN_FUNCTION(audio_sec_d0), + MSM_PIN_FUNCTION(audio_sec_d1), + MSM_PIN_FUNCTION(audio_sec_fsync), + MSM_PIN_FUNCTION(audio_sec_pclk), + MSM_PIN_FUNCTION(core_voltage_0), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(dg_out), + MSM_PIN_FUNCTION(gcc_plltest_bypassnl), + MSM_PIN_FUNCTION(gcc_plltest_resetn), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(Led00), + MSM_PIN_FUNCTION(led01), + MSM_PIN_FUNCTION(led02), + MSM_PIN_FUNCTION(led10), + MSM_PIN_FUNCTION(led11), + MSM_PIN_FUNCTION(led12), + MSM_PIN_FUNCTION(led20), + MSM_PIN_FUNCTION(led21), + MSM_PIN_FUNCTION(led22), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv0), + MSM_PIN_FUNCTION(mdc_slv1), + MSM_PIN_FUNCTION(mdc_slv2), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv0), + MSM_PIN_FUNCTION(mdio_slv1), + MSM_PIN_FUNCTION(mdio_slv2), + MSM_PIN_FUNCTION(mux_tod_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pon_active_led), + MSM_PIN_FUNCTION(pon_mux_sel), + MSM_PIN_FUNCTION(pon_rx), + MSM_PIN_FUNCTION(pon_rx_los), + MSM_PIN_FUNCTION(pon_tx), + MSM_PIN_FUNCTION(pon_tx_burst), + MSM_PIN_FUNCTION(pon_tx_dis), + MSM_PIN_FUNCTION(pon_tx_fault), + MSM_PIN_FUNCTION(pon_tx_sd), + MSM_PIN_FUNCTION(gpn_rx_los), + MSM_PIN_FUNCTION(gpn_tx_burst), + MSM_PIN_FUNCTION(gpn_tx_dis), + MSM_PIN_FUNCTION(gpn_tx_fault), + MSM_PIN_FUNCTION(gpn_tx_sd), + MSM_PIN_FUNCTION(pps), + MSM_PIN_FUNCTION(pwm_out00), + MSM_PIN_FUNCTION(pwm_out01), + MSM_PIN_FUNCTION(pwm_out02), + MSM_PIN_FUNCTION(pwm_out03), + MSM_PIN_FUNCTION(pwm_out10), + MSM_PIN_FUNCTION(pwm_out11), + MSM_PIN_FUNCTION(pwm_out12), + MSM_PIN_FUNCTION(pwm_out20), + MSM_PIN_FUNCTION(pwm_out21), + MSM_PIN_FUNCTION(pwm_out22), + MSM_PIN_FUNCTION(pwm_out30), + MSM_PIN_FUNCTION(pwm_out31), + MSM_PIN_FUNCTION(pwm_out32), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qrng_rosc0), + MSM_PIN_FUNCTION(qrng_rosc1), + MSM_PIN_FUNCTION(qrng_rosc2), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs_n), + MSM_PIN_FUNCTION(qup_se0_l0), + MSM_PIN_FUNCTION(qup_se0_l1), + MSM_PIN_FUNCTION(qup_se0_l2), + MSM_PIN_FUNCTION(qup_se0_l3), + MSM_PIN_FUNCTION(qup_se0_l4), + MSM_PIN_FUNCTION(qup_se0_l5), + MSM_PIN_FUNCTION(qup_se1_l0), + MSM_PIN_FUNCTION(qup_se1_l1), + MSM_PIN_FUNCTION(qup_se1_l2), + MSM_PIN_FUNCTION(qup_se1_l3), + MSM_PIN_FUNCTION(qup_se2_l00), + MSM_PIN_FUNCTION(qup_se2_l01), + MSM_PIN_FUNCTION(qup_se2_l10), + MSM_PIN_FUNCTION(qup_se2_l11), + MSM_PIN_FUNCTION(qup_se2_l2), + MSM_PIN_FUNCTION(qup_se2_l3), + MSM_PIN_FUNCTION(qup_se3_l0), + MSM_PIN_FUNCTION(qup_se3_l1), + MSM_PIN_FUNCTION(qup_se3_l2), + MSM_PIN_FUNCTION(qup_se3_l3), + MSM_PIN_FUNCTION(qup_se4_l0), + MSM_PIN_FUNCTION(qup_se4_l1), + MSM_PIN_FUNCTION(qup_se4_l2), + MSM_PIN_FUNCTION(qup_se4_l3), + MSM_PIN_FUNCTION(qup_se4_l4), + MSM_PIN_FUNCTION(qup_se4_l5), + MSM_PIN_FUNCTION(qup_se5_l00), + MSM_PIN_FUNCTION(qup_se5_l01), + MSM_PIN_FUNCTION(qup_se5_l10), + MSM_PIN_FUNCTION(qup_se5_l11), + MSM_PIN_FUNCTION(qup_se5_l2), + MSM_PIN_FUNCTION(qup_se5_l3), + MSM_PIN_FUNCTION(qup_se5_l4), + MSM_PIN_FUNCTION(qup_se5_l5), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx_los00), + MSM_PIN_FUNCTION(rx_los01), + MSM_PIN_FUNCTION(rx_los10), + MSM_PIN_FUNCTION(rx_los11), + MSM_PIN_FUNCTION(rx_los20), + MSM_PIN_FUNCTION(rx_los21), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(tsens_max), +}; + +static const struct msm_pingroup ipq5210_groups[] =3D { + [0] =3D PINGROUP(0, sdc_data, qspi_data, pwm_out32, _, _, _, _, _, _), + [1] =3D PINGROUP(1, sdc_data, qspi_data, pwm_out22, _, _, _, _, _, _), + [2] =3D PINGROUP(2, sdc_data, qspi_data, pwm_out12, _, _, _, _, _, _), + [3] =3D PINGROUP(3, sdc_data, qspi_data, pwm_out02, _, _, _, _, _, _), + [4] =3D PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), + [5] =3D PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + [6] =3D PINGROUP(6, qup_se0_l2, led02, pwm_out31, _, cri_trng0, qdss_trac= edata_a, _, _, _), + [7] =3D PINGROUP(7, qup_se0_l3, led12, pwm_out21, _, cri_trng1, qdss_trac= edata_a, _, _, _), + [8] =3D PINGROUP(8, qup_se0_l0, pwm_out11, audio_pri2, audio_pri2, _, cri= _trng2, qdss_tracedata_a, _, _), + [9] =3D PINGROUP(9, qup_se0_l1, led22, pwm_out01, _, cri_trng3, qdss_trac= edata_a, _, _, _), + [10] =3D PINGROUP(10, pon_rx_los, qup_se3_l3, pwm_out30, _, _, qdss_trace= data_a, _, _, _), + [11] =3D PINGROUP(11, pon_active_led, qup_se3_l2, pwm_out20, _, _, qdss_t= racedata_a, _, _, _), + [12] =3D PINGROUP(12, pon_tx_dis, qup_se2_l3, pwm_out10, audio_pri0, audi= o_pri0, _, qrng_rosc0, qdss_tracedata_a, _), + [13] =3D PINGROUP(13, gpn_tx_dis, qup_se2_l2, pwm_out00, audio_pri3, audi= o_pri3, _, qrng_rosc1, qdss_tracedata_a, _), + [14] =3D PINGROUP(14, pon_tx_burst, qup_se0_l4, _, qrng_rosc2, qdss_trace= data_a, _, _, _, _), + [15] =3D PINGROUP(15, pon_tx, qup_se0_l5, _, qdss_tracedata_a, _, _, _, _= , _), + [16] =3D PINGROUP(16, pon_tx_sd, audio_sec1, audio_sec1, qdss_cti_trig_ou= t_b0, _, _, _, _, _), + [17] =3D PINGROUP(17, pon_tx_fault, audio_sec0, audio_sec0, _, _, _, _, _= , _), + [18] =3D PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _), + [19] =3D PINGROUP(19, mux_tod_out, audio_pri1, audio_pri1, _, _, _, _, _,= _), + [20] =3D PINGROUP(20, qup_se2_l10, mdc_slv1, tsens_max, qdss_tracedata_a,= _, _, _, _, _), + [21] =3D PINGROUP(21, qup_se2_l00, mdio_slv1, qdss_tracedata_a, _, _, _, = _, _, _), + [22] =3D PINGROUP(22, core_voltage_0, qup_se3_l1, pwm_out03, _, _, _, _, = _, _), + [23] =3D PINGROUP(23, Led00, qup_se3_l0, dbg_out_clk, qdss_traceclk_a, _,= _, _, _, _), + [24] =3D PINGROUP(24, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, mdc_mst, led21, _, qdss_tracectl_a, _, _, _, _, _), + [27] =3D PINGROUP(27, mdio_mst, led11, _, _, _, _, _, _, _), + [28] =3D PINGROUP(28, pcie1_clk_req_n, qup_se1_l1, _, _, qdss_cti_trig_ou= t_a0, _, _, _, _), + [29] =3D PINGROUP(29, _, _, _, _, _, _, _, _, _), + [30] =3D PINGROUP(30, pcie1_wake, qup_se1_l0, _, _, qdss_cti_trig_in_a0, = _, _, _, _), + [31] =3D PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1,= _, _, _, _, _), + [32] =3D PINGROUP(32, _, _, _, _, _, _, _, _, _), + [33] =3D PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _= , _, _, _), + [34] =3D PINGROUP(34, audio_pri_d0, atest_char_status0, qdss_cti_trig_in_= b0, _, _, _, _, _, _), + [35] =3D PINGROUP(35, audio_pri_d1, rx_los21, atest_char_status1, qdss_ct= i_trig_out_b1, _, _, _, _, _), + [36] =3D PINGROUP(36, audio_pri_fsync, _, rx_los11, atest_char_status2, _= , _, _, _, _), + [37] =3D PINGROUP(37, audio_pri_pclk, rx_los01, atest_char_status3, _, qd= ss_cti_trig_in_b1, _, _, _, _), + [38] =3D PINGROUP(38, qup_se1_l3, led20, gcc_plltest_bypassnl, qdss_trace= data_a, _, _, _, _, _), + [39] =3D PINGROUP(39, qup_se1_l2, led10, led01, gcc_tlmm, qdss_tracedata_= a, _, _, _, _), + [40] =3D PINGROUP(40, qup_se4_l2, rx_los20, audio_sec_fsync, gcc_plltest_= resetn, qdss_tracedata_a, _, _, _, _), + [41] =3D PINGROUP(41, qup_se4_l3, rx_los10, audio_sec_pclk, qdss_tracedat= a_a, _, _, _, _, _), + [42] =3D PINGROUP(42, qup_se4_l0, rx_los00, audio_sec_d1, atest_tic_en, _= , _, _, _, _), + [43] =3D PINGROUP(43, qup_se4_l1, audio_sec_d0, _, _, _, _, _, _, _), + [44] =3D PINGROUP(44, resout, _, _, _, _, _, _, _, _), + [45] =3D PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _), + [46] =3D PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _), + [47] =3D PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5_l2, _, _, _, _, _, _), + [48] =3D PINGROUP(48, pon_rx, qup_se5_l3, _, _, _, _, _, _, _), + [49] =3D PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5_l00, audio_sec2, a= udio_sec2, _, _, _, _), + [50] =3D PINGROUP(50, gpn_tx_sd, qup_se5_l10, audio_sec3, audio_sec3, _, = _, _, _, _), + [51] =3D PINGROUP(51, gpn_tx_burst, qup_se5_l4, _, _, _, _, _, _, _), + [52] =3D PINGROUP(52, qup_se2_l11, qup_se5_l5, qup_se4_l4, qup_se5_l01, _= , _, _, _, _), + [53] =3D PINGROUP(53, qup_se2_l01, qup_se4_l5, qup_se5_l11, _, _, _, _, _= , _), +}; + +static const struct msm_pinctrl_soc_data ipq5210_tlmm =3D { + .pins =3D ipq5210_pins, + .npins =3D ARRAY_SIZE(ipq5210_pins), + .functions =3D ipq5210_functions, + .nfunctions =3D ARRAY_SIZE(ipq5210_functions), + .groups =3D ipq5210_groups, + .ngroups =3D ARRAY_SIZE(ipq5210_groups), + .ngpios =3D 54, +}; + +static const struct of_device_id ipq5210_tlmm_of_match[] =3D { + { .compatible =3D "qcom,ipq5210-tlmm", }, + { }, +}; + +static int ipq5210_tlmm_probe(struct platform_device *pdev) +{ + return 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Signed-off-by: Kathiravan Thirumoorthy Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d95acd4a424d368a481aa49d66449f784cf81986..9bf291511bc8910f0118e2e804c= 07c02770d5fd1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -309,6 +309,11 @@ properties: - tplink,archer-ax55-v1 - const: qcom,ipq5018 =20 + - items: + - enum: + - qcom,ipq5210-rdp504 + - const: qcom,ipq5210 + - items: - enum: - qcom,ipq5332-ap-mi01.2 --=20 2.34.1 From nobody Tue Apr 7 22:04:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF1583C457D for ; Wed, 11 Mar 2026 09:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Add the appropriate compatible to the documentation. Signed-off-by: Kathiravan Thirumoorthy Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 938be8228d668c87f0be95c63d4d951ebbadd4e4..fd1d5b04e7556903daffe86e455= fde11be0dbd9f 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -38,6 +38,7 @@ properties: - items: - enum: - qcom,ipq5018-sdhci + - qcom,ipq5210-sdhci - qcom,ipq5332-sdhci - qcom,ipq5424-sdhci - qcom,ipq6018-sdhci --=20 2.34.1 From nobody Tue Apr 7 22:04:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C7723C5DC0 for ; Wed, 11 Mar 2026 09:46:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index d66459f1d84e4d99c7f72415d08bfdaf1d701948..6d9b71a9b9b3fefd1951b963f34= 942243aa48ccb 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -26,6 +26,7 @@ properties: - qcom,scm-glymur - qcom,scm-ipq4019 - qcom,scm-ipq5018 + - qcom,scm-ipq5210 - qcom,scm-ipq5332 - qcom,scm-ipq5424 - qcom,scm-ipq6018 --=20 2.34.1 From nobody Tue Apr 7 22:04:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF39022339 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df5ff0sm1677403b3a.21.2026.03.11.02.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 02:46:39 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 11 Mar 2026 15:15:50 +0530 Subject: [PATCH 8/9] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-ipq5210_boot_to_shell-v1-8-fe857d68d698@oss.qualcomm.com> References: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> In-Reply-To: <20260311-ipq5210_boot_to_shell-v1-0-fe857d68d698@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Linus Walleij , Konrad Dybcio , Ulf Hansson , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mmc@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773222347; l=10487; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=dlSRQRF023jUCsl4IbZQYSPJTNojRWXNTDfxc219h60=; b=qIko03d3wIkBuaJSeXL1R9YQKDCjfVPfJVR4ZnzgiUwI6+6g9dbjOoTKOItDFJ4JJ9SbEo2MR Q+O+XozkBTODSw38ebYhPY+EpvoEuDKPoxjEHDBoigTr+Y3rArztMz8 X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4MSBTYWx0ZWRfX/cKYLoAarv3N dGP5Ol8LL8kOovdcWUCFVgiEzNZO9YPZFjRg46rYjyb070Q1rIy6KTbH/RDektbxaG3jEwHNFQQ dpVWBAlBeOXRdIL4DoC4gmzGWTVVgJZF0QJ/lI9diL5jSH/scVutOHPiNGE/5OZZMFoBBwW4PV8 LUlo+TZx8Ps8c+gzG3NiWEIndNSGS4A/+oQWLVzAbyuiWkrxFmstHwYMk3/iCp9Ab4bPZRJmOYh UqUV0XCB+eB2/erk8yD5pXEsbwJzydAhFFbif+18+SeUpQlBmvyeAu2K6+h1fmnwlW1k/kK+h+c UBJCjO6uYiILJVO8GD+sjMkcT/iE9l/VU0v+iBQLZ2Mu9o0ogTbihpd4GnQG3oUXOOymkV8xSNc i+4E5lc9EZJAfcxgbF+mWHoDup1MzphCLjTJINfIBWP02XrUGNpSBknOSF7M2espAf9RjuPVkHH RrXmjeDtfgEWtn47mpQ== X-Proofpoint-ORIG-GUID: iRc-f8-dtHPf2r9K7v8BKIDdf0Pe5S3D X-Authority-Analysis: v=2.4 cv=Lo2fC3dc c=1 sm=1 tr=0 ts=69b13a01 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=fBkTXTPqfNaV2XDYC8MA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: iRc-f8-dtHPf2r9K7v8BKIDdf0Pe5S3D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110081 Add initial device tree support for the Qualcomm IPQ5210 SoC and rdp504 board. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 93 +++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 304 ++++++++++++++++++++++++= ++++ 3 files changed, 398 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 02921a495b2cbabcbacc74fbbb99eafe1f6478ac..e7748af640cccffa5c83ec82c37= aa441444c2b13 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -22,6 +22,7 @@ hamoa-iot-evk-el2-dtbs :=3D hamoa-iot-evk.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5210-rdp504.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts new file mode 100644 index 0000000000000000000000000000000000000000..3d95939785bc5bd4f510e2f992f= 0a1e80848c8de --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + compatible =3D "qcom,ipq5210-rdp504", "qcom,ipq5210"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0"; + }; + + soc@0 { + qupv3: geniqup@1ac0000 { + status =3D "okay"; + + uart1: serial@1a84000 { + pinctrl-0 =3D <&qup_uart1_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; + }; + }; + }; +}; + +&sdhc { + max-frequency =3D <192000000>; + bus-width =3D <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 =3D <&sdhc_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + tx-pins { + pins =3D "gpio39"; + function =3D "qup_se1_l2"; + drive-strength =3D <6>; + bias-pull-down; + }; + + rx-pins { + pins =3D "gpio38"; + function =3D "qup_se1_l3"; + drive-strength =3D <6>; + bias-pull-down; + }; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; +}; + +&xo { + clock-frequency =3D <24000000>; +}; + diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b959162737c87d8c44fd18cd7e9= 54f85f797085a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo: xo { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + L2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <0x2>; + cache-unified; + }; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scm { + compatible =3D "qcom,scm-ipq5210", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + bootloader@87800000 { + reg =3D <0x0 0x87800000 0x0 0x400000>; + no-map; + }; + + smem@87c00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x87c00000 0x0 0x40000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + tfa@87d00000 { + reg =3D <0x0 0x87d00000 0x0 0x80000>; + no-map; + }; + + optee@87d80000 { + reg =3D <0x0 0x87d80000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq5210-tlmm"; + reg =3D <0x0 0x01000000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq5210-gcc"; + reg =3D <0x0 0x01800000 0x0 0x40000>; + clocks =3D <&xo>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01905000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + status =3D "disabled"; + + uart1: serial@1a84000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_SE1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible =3D "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names =3D "iface", + "core", + "xo"; + non-removable; + status =3D "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0 0xb000000 0x0 0x1000>, /* GICD */ + <0x0 0xb002000 0x0 0x1000>, /* GICC */ + <0x0 0xb001000 0x0 0x1000>, /* GICH */ + <0x0 0xb004000 0x0 0x1000>; /* GICV */ + interrupts =3D ; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x0b00c000 0 0x3000>; + + v2m0: v2m@0 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x0 0x0 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x00001000 0x0 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x00002000 0x0 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0xb120000 0x0 0x1000>; + ranges =3D <0 0 0 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@b121000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0b123000 0x1000>; + status =3D "disabled"; + }; + + frame@b124000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0b124000 0x1000>; + status =3D "disabled"; + }; + + frame@b125000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0b125000 0x1000>; + status =3D "disabled"; + }; + + frame@b126000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0b126000 0x1000>; + status =3D "disabled"; + }; + + frame@b127000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0b127000 0x1000>; + status =3D "disabled"; + }; + + frame@b128000 { + frame-number =3D <6>; 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Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ed70ab7ee854038fa7a756d8b650a609258bdb3..59c748efc1ca8d6eb7dca19011d= 2a31d926a0d43 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -649,6 +649,7 @@ CONFIG_PINCTRL_IMX_SCMI=3Dy CONFIG_PINCTRL_MSM=3Dy CONFIG_PINCTRL_GLYMUR=3Dy CONFIG_PINCTRL_IPQ5018=3Dy +CONFIG_PINCTRL_IPQ5210=3Dy CONFIG_PINCTRL_IPQ5332=3Dy CONFIG_PINCTRL_IPQ5424=3Dy CONFIG_PINCTRL_IPQ8074=3Dy @@ -1476,6 +1477,7 @@ CONFIG_IPQ_APSS_6018=3Dy CONFIG_IPQ_APSS_5018=3Dy CONFIG_IPQ_CMN_PLL=3Dm CONFIG_IPQ_GCC_5018=3Dy +CONFIG_IPQ_GCC_5210=3Dy CONFIG_IPQ_GCC_5332=3Dy CONFIG_IPQ_GCC_5424=3Dy CONFIG_IPQ_GCC_6018=3Dy --=20 2.34.1