From nobody Thu Apr 9 05:49:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ECF837703D; Wed, 11 Mar 2026 07:54:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215642; cv=none; b=jiucU1Gv8PMVPwst1kFhv7UcXiNPBAGumhFL5z9gU3m4ygTKIGbTjkr9Q/xmyYuk5sj+lmvkU687vYkHr4dHTtslEkFbjSe6mitiNaPZG2fR11k8pvgOa5FAkaV9nZS4cVZahXP8MRNuAmVwdp5S6lXRYdzC2bv/aWIkBnOmbnc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773215642; c=relaxed/simple; bh=t5KwaNb/RUlMNvnjAQljSY30lTI+e060jlUtQ9txKe8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iHmo/tMBOj8S6oZi8qAZby4uu6to0albgMAcYb4NosaVuEGbu7h3wlo/4EvVRZtaTS5ZnKXgXlHmKAAMk1G/8UpeCGf/mMfzHFoLoR1E6UCXj6ZP+rmIgfgSMOujInHZamkS1hEdaBwU1EgHNgY1FJshTuI7jfv+Ws021WEnNbg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ADrYACeI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ADrYACeI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 22C6CC2BCB2; Wed, 11 Mar 2026 07:54:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773215642; bh=t5KwaNb/RUlMNvnjAQljSY30lTI+e060jlUtQ9txKe8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ADrYACeIJZX/4IqeOB2IRx17qhRDNFEJGEUbURBm0fI8ybt6Ozx4N9093q/MCWDLD 3C1vKTmDuqxoelRoJ7RjTaUiwvLTKkOw9WMudR2ydrH2rYYeRVyhP0C54DWmKJrOQN WaMXXbg2ayNhwhA+HVuSI5vEuNaYAVIEYQsWddcLyhHOplH3w3QyrzNxrhby301Uxx aYLJLKovq4Makkx0suMD/YgHsyzXfuofEtOLyULW4LRWUq6TC/UWEVPhmA7lBt8tLZ 7iYz6pMZ9CuRpl5UozKIeYkgaj/ieLkrzfkM0FVRqm7KM4mx7+VteR46iZU6wKSNlh A5gjKgDH3Cr7A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11159FD0648; Wed, 11 Mar 2026 07:54:02 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 11 Mar 2026 08:53:58 +0100 Subject: [PATCH v9 3/5] arm64: dts: s32: set Ethernet channel irqs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-dwmac_multi_irq-v9-3-f0c03ef8d01f@oss.nxp.com> References: <20260311-dwmac_multi_irq-v9-0-f0c03ef8d01f@oss.nxp.com> In-Reply-To: <20260311-dwmac_multi_irq-v9-0-f0c03ef8d01f@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773215640; l=4163; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=GJtLVXXJ6B4rcW9eI+Zdnzjbg44iN/frnopr12Ti4EU=; b=eJUTqcie0RXcVx8brTOdzgrPB5fI1SjmlsdnCrFneGpms8Wm7ot6TNpqx+1E211nM12CCopQP AjK8s7pMF3BCQ6LQ+pK7aJsjQZXiTV7e8mpPM1l9Gs9TeEEp/h4p5dR X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The GMAC Ethernet controller found on S32G2/S32G3 and S32R45 contains up to 5 RX and 5 TX channels. It can operate in two interrupt modes: 1) Sharing IRQ mode: only MAC IRQ line is used for all channels. 2) Multiple IRQ mode: every channel uses two IRQ lines, one for RX and second for TX. Specify all IRQ twins for all channels. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++--- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..5a553d503137 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index e314f3c7d61d..b43e6f001f4d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; --=20 2.47.0