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Use the preferred form over "reset-gpio" deprecated since commit 42694f9f6407 ("dt-bindings: PCI: add snps,dw-pcie.yaml") in 2021. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- 17 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/a= rch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index ea1d5b9c6bae..5642139ebaec 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -301,7 +301,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 21 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 21 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/= arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 472c584fb3bd..6a874f3ec22a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -919,7 +919,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio1 5 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boo= t/dts/freescale/imx8mm-evk.dtsi index 8be44eaf4e1e..31052ca1971e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -533,7 +533,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 21 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 21 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi index 299752aa8277..7eca9127bb9e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi @@ -209,7 +209,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio5 21 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio5 21 GPIO_ACTIVE_LOW>; fsl,max-link-speed =3D <1>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_C= TRL>; assigned-clock-rates =3D <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts b/arch/ar= m64/boot/dts/freescale/imx8mm-iot-gateway.dts index 370558a8ba46..e5b8415dbe0f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts @@ -137,7 +137,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio3 20 GPIO_ACTIVE_LOW>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/= arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 6043e7d16306..0165ae04c6ae 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -205,7 +205,7 @@ &pcie0 { assigned-clock-rates =3D <10000000>, <250000000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie>; - reset-gpio =3D <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 9 GPIO_ACTIVE_LOW>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arc= h/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index 2ecc8b3c67da..a5f3dfe06a4a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -182,7 +182,7 @@ &pcie0 { assigned-clock-rates =3D <10000000>, <100000000>, <250000000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie>; - reset-gpio =3D <&gpio3 22 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio3 22 GPIO_ACTIVE_LOW>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index 8dcc5cbcb8f6..ce785b103a57 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -90,7 +90,7 @@ &pcie_phy { =20 /* PCIe slot on X36 */ &pcie0 { - reset-gpio =3D <&expander0 14 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&expander0 14 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 320806d3d073..bb441fd4aa23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -122,7 +122,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 6 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 266038fbbef9..184fdfb26cd5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -147,7 +147,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 6 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 2aa6c1090fc7..1e84c365b2cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -167,7 +167,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 6 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi index 53004c4a13aa..e0982b4cb663 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi @@ -152,7 +152,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 6 GPIO_ACTIVE_LOW>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/= arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 272c2b223d16..a31bd864c022 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -726,7 +726,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio5 2 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio5 2 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/= arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 468c7e993c52..4c839dfa3ce0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -626,7 +626,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio4 5 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 5 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/= arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 636daa3d6ca2..ea67654c9ded 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -559,7 +559,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio5 11 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/= arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index 99572961d9e1..7028d028657a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -623,7 +623,7 @@ &pcie_phy { &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; - reset-gpio =3D <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio5 11 GPIO_ACTIVE_LOW>; clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/= boot/dts/freescale/imx8mm-verdin.dtsi index 1594ce9182a5..3b656f8a81b6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -672,7 +672,7 @@ &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pcie0>; /* PCIE_1_RESET# (SODIMM 244) */ - reset-gpio =3D <&gpio3 19 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio3 19 GPIO_ACTIVE_LOW>; }; =20 &pcie_phy { --=20 2.51.0