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Wed, 11 Mar 2026 03:26:59 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aeae222872sm19575245ad.18.2026.03.11.03.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 03:26:59 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Wed, 11 Mar 2026 15:56:46 +0530 Subject: [PATCH v3 1/5] PCI: host-common: Add helper to determine host bridge D3cold eligibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-d3cold-v3-1-4d85dc7c2695@oss.qualcomm.com> References: <20260311-d3cold-v3-0-4d85dc7c2695@oss.qualcomm.com> In-Reply-To: <20260311-d3cold-v3-0-4d85dc7c2695@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This helper is intended to be used by PCI host controller drivers to decide whether they may safely put the host bridge into D3cold based on the power state and wakeup capabilities of downstream endpoints. The helper walks all devices on the bridge's primary bus and only allows the host bridge to enter D3cold if all PCIe endpoints are already in PCI_D3hot. This ensures that we do not power off the host bridge while any active endpoint still requires the link to remain powered. For devices that may wake the system, the helper additionally requires that the device supports PME wake from D3cold (via WAKE#). Devices that do not have wakeup enabled are not restricted by this check and do not block the host bridge from entering D3cold. Devices without a bound driver and with PCI not enabled via sysfs are treated as inactive and therefore do not prevent the host bridge from entering D3cold. This allows controllers to power down more aggressively when there are no actively managed endpoints. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/pci-host-common.c | 47 ++++++++++++++++++++++++++++= ++++ drivers/pci/controller/pci-host-common.h | 2 ++ 2 files changed, 49 insertions(+) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/control= ler/pci-host-common.c index d6258c1cffe5ec480fd2a7e50b3af39ef6ac4c8c..bff23bcdb5d032d2781d963eebe= 4a3fac0505517 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -106,5 +106,52 @@ void pci_host_common_remove(struct platform_device *pd= ev) } EXPORT_SYMBOL_GPL(pci_host_common_remove); =20 +static int __pci_host_common_d3cold_possible(struct pci_dev *pdev, void *u= serdata) +{ + bool *d3cold_possible =3D userdata; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return 0; + + if (!pdev->dev.driver && !pci_is_enabled(pdev)) + return 0; + + if (pdev->current_state !=3D PCI_D3hot) + goto exit; + + if (device_may_wakeup(&pdev->dev) && !pci_pme_capable(pdev, PCI_D3cold)) + goto exit; + + return 0; + +exit: + *d3cold_possible =3D false; + + return -EOPNOTSUPP; +} + +/** + * pci_host_common_d3cold_possible - Determine whether a host bridge can e= nter D3cold + * @bridge: PCI host bridge to check + * + * Walk downstream PCIe endpoint devices and determine whether the host br= idge + * is permitted to transition to D3cold. + * + * The host bridge can enter D3cold only if all active PCIe endpoints are = in + * PCI_D3hot and any wakeup-enabled endpoint is capable of generating PME = from + * D3cold. Inactive endpoints are ignored. + * + * Return: %true if the host bridge may enter D3cold, otherwise %false. + */ +bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge) +{ + bool d3cold_allow =3D true; + + pci_walk_bus(bridge->bus, __pci_host_common_d3cold_possible, &d3cold_allo= w); + + return d3cold_allow; +} +EXPORT_SYMBOL_GPL(pci_host_common_d3cold_possible); + MODULE_DESCRIPTION("Common library for PCI host controller drivers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/control= ler/pci-host-common.h index b5075d4bd7eb31fbf1dc946ef1a6afd5afb5b3c6..c0ef2a2bf3994ce66686b3f8eae= 25538f3a902b4 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -20,4 +20,6 @@ void pci_host_common_remove(struct platform_device *pdev); =20 struct pci_config_window *pci_host_common_ecam_create(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); + +bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge); 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However, such devices typically remain in D0 and are already covered by the new helper's requirement that all endpoints be in D3hot before the host bridge may enter D3cold. So, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with the shared pci_host_common_d3cold_possible() helper to decide whether the DesignWare host bridge can safely transition to D3cold. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 6ae6189e9b8a9021c99ece17504834650debd86b..8e81f0208c76fb22aa908de4e1f= f379ec0cae2ff 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -16,9 +16,11 @@ #include #include #include +#include #include #include =20 +#include "../pci-host-common.h" #include "../../pci.h" #include "pcie-designware.h" =20 @@ -1218,18 +1220,13 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) =20 int dw_pcie_suspend_noirq(struct dw_pcie *pci) { - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int ret =3D 0; u32 val; =20 if (!dw_pcie_link_up(pci)) goto stop_link; =20 - /* - * If L1SS is supported, then do not put the link into L2 as some - * devices such as NVMe expect low resume latency. - */ - if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM= _L1) + if (!pci_host_common_d3cold_possible(pci->pp.bridge)) return 0; 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Wed, 11 Mar 2026 03:27:08 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aeae222872sm19575245ad.18.2026.03.11.03.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 03:27:07 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Wed, 11 Mar 2026 15:56:48 +0530 Subject: [PATCH v3 3/5] PCI: qcom: Add .get_ltssm() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260311-d3cold-v3-3-4d85dc7c2695@oss.qualcomm.com> References: <20260311-d3cold-v3-0-4d85dc7c2695@oss.qualcomm.com> In-Reply-To: <20260311-d3cold-v3-0-4d85dc7c2695@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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To avoid unsafe DBI accesses, introduce qcom_pcie_get_ltssm(), which retrieves the LTSSM state from the PARF_LTSSM register instead. This helper is used in place of direct DBI-based link state checks in the D3cold path after sending PME turn-off message, ensuring the LTSSM state can be queried safely even after DBI access is no longer valid. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 67a16af69ddc75fca1b123e70715e692a91a9135..b00bf46637a5ff803a845719c5b= 0b5b82739244b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -131,6 +131,7 @@ =20 /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +#define PARF_LTSSM_STATE_MASK GENMASK(5, 0) =20 /* PARF_NO_SNOOP_OVERRIDE register fields */ #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) @@ -1255,6 +1256,16 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci) return val & PCI_EXP_LNKSTA_DLLLA; } =20 +static enum dw_pcie_ltssm qcom_pcie_get_ltssm(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u32 val; + + val =3D readl(pcie->parf + PARF_LTSSM); + + return (enum dw_pcie_ltssm)FIELD_GET(PARF_LTSSM_STATE_MASK, val); +} + static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) { struct qcom_pcie_port *port; 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When the link is later transitioned towards D3cold and the driver disables PCIe clocks and/or regulators without explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain partially powered, leading to avoidable power leakage. Update the init-path comments to reflect that PARF_PHY_CTRL is used to power the PHY on. Also, for controller revisions that enable PHY power in init (2.3.2, 2.3.3, 2.7.0 and 2.9.0), explicitly power the PHY down via PARF_PHY_CTRL in the deinit path before disabling clocks/regulators. This ensures the PHY is put into a defined low-power state prior to removing its supplies, preventing leakage when entering D3cold. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 32 +++++++++++++++++++++++++++++-= -- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b00bf46637a5ff803a845719c5b0b5b82739244b..c14c3eb70f356b6ad8a2ffe48b1= 07327d2babf77 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -513,7 +513,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) u32 val; int ret; =20 - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -680,6 +680,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_p= cie *pcie) static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res =3D &pcie->res.v2_3_2; + u32 val; + + /* Force PHY to lowest power state*/ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -712,7 +718,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *= pcie) { u32 val; =20 - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -844,6 +850,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_p= cie *pcie) static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; + u32 val; + + /* Force PHY to lowest power state */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -899,6 +911,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *= pcie) u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; =20 + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -994,7 +1007,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 - /* enable PCIe clocks and resets */ + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1065,6 +1078,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qc= om_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; + u32 val; + + /* Force PHY to lowest power state */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); =20 @@ -1169,6 +1188,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom= _pcie *pcie) static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res =3D &pcie->res.v2_9_0; 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a=ed25519-sha256; t=1773224811; l=6534; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=0v4Fkx+XZDjpsl3JOqkuJUc5cmWHZo8Xz0ri4m2aC0w=; b=SnIVcO4hLWZtCxfU7w8+oUn/qP8keFHFwEx8hZLsyGowOrb4LgEnu6sFoJS0pWt49wuPjv9rq wJHOkis+50XBeK+3nsfQvv9kOH6UvijOD9DQ7+BO/iBiHtFa7TKjEYz X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: JCNEJwurW8VPHZvmfb8RgJGizvEhuIrc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA4NyBTYWx0ZWRfX+uxkK4IKTyTw 2Vq3wvs7ubEUoFhcy8xksKs4Md0YFFpWwNBtxhbd2mdYyHlmLUbqpcSrq3V6tfCqgLwIic8mdbl 0pOXdt2yP2+knIl0BbSk2zrhgsVFYFovSMVUIdy8gaxNhlxkpIXKe479stLaq8gu6xxRd3l2pW2 qMmxTilm1HWZ8WHw9qceJL9zuAa6VKTkxVbVCjqBNO8zrZz6gj5fTA+ZzlDSRxSUAuYT4RACp2E tfVXllkrlFkfHGwfuswvH4Pc+YtfKi351UcBW4my/pmASObycUI/uquSShhT57GnCZVFcAUEYwP 5w2IGJqK7AD9BnShsLm7gcqEwGd1AsJhfW6UOY/rdQrNWXSkRChDPD6pVyEA/uDS8aBYloeSMM0 oQ27Idw2nVbr5LqOgR9eq3B8cQ92Q6xPLwfOtuTvaz5V3j1WLdKou6Rd2gJzlTQKvZpi1EJJchP PyU3/yJHMbrwzI8AeMA== X-Proofpoint-ORIG-GUID: JCNEJwurW8VPHZvmfb8RgJGizvEhuIrc X-Authority-Analysis: v=2.4 cv=Gq5PO01C c=1 sm=1 tr=0 ts=69b14386 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=RN3yzfvplrNe8VIVIhoA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110087 Add support for transitioning PCIe endpoints & bridges into D3cold by integrating with the DWC core suspend/resume helpers. Implement PME_TurnOff message generation via ELBI_SYS_CTRL and hook it into the DWC host operations so the controller follows the standard PME_TurnOff-based power-down sequence before entering D3cold. When the device is suspended into D3cold, fully tear down interconnect bandwidth, OPP votes. If D3cold is not entered, retain existing behavior by keeping the required interconnect and OPP votes. Drop the qcom_pcie::suspended flag and rely on the existing dw_pcie::suspended state, which now drives both the power-management flow and the interconnect/OPP handling. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 121 ++++++++++++++++++++---------= ---- 1 file changed, 74 insertions(+), 47 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index c14c3eb70f356b6ad8a2ffe48b107327d2babf77..6c5e9e541d55ad7f90a2203b978= 47d15d56b59c3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -145,6 +145,7 @@ =20 /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) =20 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 @@ -283,7 +284,6 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; struct list_head ports; - bool suspended; bool use_pm_opp; }; =20 @@ -1404,10 +1404,18 @@ static void qcom_pcie_host_post_init(struct dw_pcie= _rp *pp) pcie->cfg->ops->host_post_init(pcie); } =20 +static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + + writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, .post_init =3D qcom_pcie_host_post_init, + .pme_turn_off =3D qcom_pcie_host_pme_turn_off, }; =20 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -2072,53 +2080,51 @@ static int qcom_pcie_suspend_noirq(struct device *d= ev) if (!pcie) return 0; =20 - /* - * Set minimum bandwidth required to keep data path functional during - * suspend. - */ - if (pcie->icc_mem) { - ret =3D icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); - if (ret) { - dev_err(dev, - "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", - ret); - return ret; - } - } + ret =3D dw_pcie_suspend_noirq(pcie->pci); + if (ret) + return ret; =20 - /* - * Turn OFF the resources only for controllers without active PCIe - * devices. For controllers with active devices, the resources are kept - * ON and the link is expected to be in L0/L1 (sub)states. - * - * Turning OFF the resources for controllers with active PCIe devices - * will trigger access violation during the end of the suspend cycle, - * as kernel tries to access the PCIe devices config space for masking - * MSIs. - * - * Also, it is not desirable to put the link into L2/L3 state as that - * implies VDD supply will be removed and the devices may go into - * powerdown state. This will affect the lifetime of the storage devices - * like NVMe. - */ - if (!dw_pcie_link_up(pcie->pci)) { - qcom_pcie_host_deinit(&pcie->pci->pp); - pcie->suspended =3D true; - } + if (pcie->pci->suspended) { + ret =3D icc_disable(pcie->icc_mem); + if (ret) + dev_err(dev, "Failed to disable PCIe-MEM interconnect path: %d\n", ret); =20 - /* - * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. - * Because on some platforms, DBI access can happen very late during the - * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC - * error. - */ - if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { ret =3D icc_disable(pcie->icc_cpu); if (ret) dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); =20 if (pcie->use_pm_opp) dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } else { + /* + * Set minimum bandwidth required to keep data path functional during + * suspend. + */ + if (pcie->icc_mem) { + ret =3D icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + if (ret) { + dev_err(dev, + "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + } + + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + ret =3D icc_disable(pcie->icc_cpu); + if (ret) + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", + ret); + + if (pcie->use_pm_opp) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); + } } return ret; } @@ -2132,25 +2138,46 @@ static int qcom_pcie_resume_noirq(struct device *de= v) if (!pcie) return 0; =20 - if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + if (pcie->pci->suspended) { ret =3D icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); return ret; } - } =20 - if (pcie->suspended) { - ret =3D qcom_pcie_host_init(&pcie->pci->pp); - if (ret) - return ret; + ret =3D icc_enable(pcie->icc_mem); + if (ret) { + dev_err(dev, "Failed to enable PCIe-MEM interconnect path: %d\n", ret); + goto disable_icc_cpu; + } =20 - pcie->suspended =3D false; + /* + * Ignore -ENODEV & -EIO here since it is expected when no endpoint is + * connected to the PCIe link. + */ + ret =3D dw_pcie_resume_noirq(pcie->pci); + if (ret && ret !=3D -ENODEV && ret !=3D -EIO) + goto disable_icc_mem; + } else { + if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + ret =3D icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", + ret); + return ret; + } + } } =20 qcom_pcie_icc_opp_update(pcie); =20 return 0; +disable_icc_mem: + icc_disable(pcie->icc_mem); +disable_icc_cpu: + icc_disable(pcie->icc_cpu); + + return ret; } =20 static const struct of_device_id qcom_pcie_match[] =3D { --=20 2.34.1