From nobody Tue Apr 7 21:42:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03D323DF018; Wed, 11 Mar 2026 15:17:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773242279; cv=none; b=q286ucLnhO+6S/CGSuvVKadB1v6jnChGOcRxBB3DGzkACtp0CDhJ9pAbXJMe2zyDUQoMXbR5OwcC25jvyNH8Pscbm42PumMpRgQ0HyZUK5jN/BtbqEdVxxGjDpNLMiKSPgP6+3sVfFDicEjNqaIq1XFsvBHgll6rHSIsZ31Wsvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773242279; c=relaxed/simple; bh=3iLbeXMaAFchbBwKQKm1kXam41pf4wI0Ggn8ouFfieg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qQwrT2uvD5vDPKOqMwgt/L9TWfMTtJxB9LD8p9EofOFEBbnRm3Br2GA15+PKV8MeNtDyV7+4He825Hwg9ggoVWaxmwioqE8uVoYhYMonkOmMvYmYRqQvtq1mznxl0bNjMUTFvmtFbJeHob/n+HbT1ZdBzWY9kyr2KbiQVx3IaFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bCdMmoWY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bCdMmoWY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A3D45C4CEF7; Wed, 11 Mar 2026 15:17:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773242278; bh=3iLbeXMaAFchbBwKQKm1kXam41pf4wI0Ggn8ouFfieg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bCdMmoWYk5+FUC/2S7+7REdmO8TvVB4RzOueEjNCn268vYCw0AbBfgBnM7iWoE6P6 loCimgZ35w3YNEfoxEXMOAktXdO/Nq7czQDk5ZMsCaWKdposQfD1sB/PCUFBE2SBLv i7dKgjA4IUovhKKMM1/o4PU+9dQtp/mNV2yJgjOghJdanujxXo69DiTXN3cmiktyhH Uu2mkmmB8uRjGImFe6Ci7elpey4OJl9UtJkmf3/fUHjEdEZ8i+85nQKzESJBRXasGm xaVmxowaClNFo6ac8eLJuV5681dbjK7LJ84py/VW/v4beH+gZ68LsnbRPyN+Nv2qzm 6l9/f51wx6Hqw== From: Conor Dooley To: linux-gpio@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Thomas Gleixner , Herve Codina , Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v12 2/4] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux Date: Wed, 11 Mar 2026 15:17:39 +0000 Message-ID: <20260311-collar-smokiness-5313aa648a6f@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260311-tasting-friend-eae39148fb96@spud> References: <20260311-tasting-friend-eae39148fb96@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3934; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=RN7LDQFkYU3/9fCUf4/UYFIw43RG2HuAYTNsTKPwK8I=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkb26c3vO3nnn0p+txvK2lrM0mBv+Ydyz5xuu5P1wz/4 3GltvJ+RykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbyfz7DX5l7Ij5vE3pyI9k6 FZVOx/T1W7zXkXUyXbK1stRJXvfJe4b/ceb7OOecYxBwsgg6m3Pk+48lVWlP6tctOL/C5tI8xTR rXgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Reviewed-by: Herve Codina Signed-off-by: Conor Dooley --- .../soc/microchip/microchip,mpfs-irqmux.yaml | 77 +++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 4 + 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-irqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mp= fs-irqmux.yaml new file mode 100644 index 0000000000000..6a743b5067f75 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux= .yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-irqmux.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire SoC GPIO Interrupt Mux + +maintainers: + - Conor Dooley + +description: | + There are 3 GPIO controllers on this SoC, of which: + - GPIO controller 0 has 14 GPIOs + - GPIO controller 1 has 24 GPIOs + - GPIO controller 2 has 32 GPIOs + + All GPIOs are capable of generating interrupts, for a total of 70. + There are only 41 IRQs available however, so a configurable mux is used = to + ensure all GPIOs can be used for interrupt generation. + 38 of the 41 interrupts are in what the documentation calls "direct mode= ", + as they provide an exclusive connection from a GPIO to the PLIC. + Lines 18 to 23 on GPIO controller 1 are always in "direct mode". + The 3 remaining interrupts are used to mux the interrupts which do not h= ave + a exclusive connection, one for each GPIO controller. + +properties: + compatible: + const: microchip,mpfs-irqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: | + Specifies the mapping from GPIO interrupt lines to plic interrupts. + + The child interrupt number set in arrays items is computed using the + following formula: + gpio_bank * 32 + gpio_number + with: + - gpio_bank: The GPIO bank number + - 0 for GPIO0, + - 1 for GPIO1, + - 2 for GPIO2 + - gpio_number: Number of the gpio in the bank (0..31) + maxItems: 70 + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + interrupt-controller@54 { + compatible =3D "microchip,mpfs-irqmux"; + reg =3D <0x54 0x4>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0xff>; + }; diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 44e4a50c31554..276d48ba15f01 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -38,6 +38,10 @@ properties: of PolarFire clock/reset IDs. const: 1 =20 + interrupt-controller@54: + type: object + $ref: /schemas/soc/microchip/microchip,mpfs-irqmux.yaml + pinctrl@200: type: object $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml --=20 2.51.0