From nobody Thu Apr 9 07:16:34 2026 Received: from mail-wm1-f73.google.com (mail-wm1-f73.google.com [209.85.128.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81E303A5448 for ; Tue, 10 Mar 2026 12:49:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773146992; cv=none; b=PNi3eKaCd/0VNIEcbL8M8HfTCTe5n2/htG7CEBBOQhdxLynk3+ZNUD+PqEQ50WJ4JK2P53dwdeWNDCwouiFF+7IBwswOjCzGHiTKn8r3LtKkqUOwoOJs5ev5sCrtnHU2MQNKZTZr+l9F4HA2n+k9A3QN2BlejEyu7zSePRXh4cw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773146992; c=relaxed/simple; bh=FR2M+E90Y1v5dC4HO5pEPtueuObDehuxAUbp0SHmBiQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Ubi4Zq47vqS1xZHjA/T+JapED1mDFMl8pqViwT2RxX6+d+7Bbumiot8l0ZxSjabBDoy9+9hugRapzqTc4bVgYztZVGSJe49I5VXOnVUhm9S/D/Aq9DgwYUl4DyDFM9/8MDYHXUTyc0w1nxMAhqvhguDiM3hU/Lv+RsMHU2CziVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--sebastianene.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=z5q5ntKk; arc=none smtp.client-ip=209.85.128.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--sebastianene.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="z5q5ntKk" Received: by mail-wm1-f73.google.com with SMTP id 5b1f17b1804b1-4853efceaddso15498515e9.3 for ; Tue, 10 Mar 2026 05:49:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1773146988; x=1773751788; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=IBw8//o/FKk+iSUCDuIRcFnfCH+1hN6m93POT/Oa1kE=; b=z5q5ntKkzoWVwqAChirkfH6/5TLkLiveNkngJibNKadHKa2PIl9JRgVEByhKc0cDMs /YhyH8ESwO1uw2lESEndclA1SapykexReqzcaDdpCj0MOzdQS9Xa4Zs2ZT/D1cQfFJBx 8dFVdr0/OdTxkApMDQ66eMv6c6mq46Ebql7ndSpUU7/qLVwLHng5GZBPzaY1LANWSuxv YXLHV2Bc2rrfXV1bcxlsgNMuKBarBTpgl5FtdKRvYSgUS7tPXTpgRUblSpm2Qf35GUxJ PzKCW8IlESVXg3jqhgF+G82x5DzH2hVTc8qnLaHdWsgElmawqqc4nrpzD2ZK9UOskRcj NIrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773146988; x=1773751788; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=IBw8//o/FKk+iSUCDuIRcFnfCH+1hN6m93POT/Oa1kE=; b=FdZgXHczavjRYibHckYM/0tpuD3FDPD0y7bSzgqcZxeSjNkUHgzUNYAZ9Yk2F+Oslv f10mqes2igEZDsuGm11Y7sikB0QCIX6aKXBE06sHg+qHAwreLuddY4E6U+pTPnn5oSXg NdxrxkOR93Nlyxuz/ioN3ZkYobwQ6ZjLOfchguDlJcjsDbY5kJQeA5dFR7pSpfCIni9o qjsrU2Aduvykfd7pidICau5i2kLSSKGfjFajaEvfEF0gW7MEZk5k8ctrfl0u6rudhmg0 aR4cIwTFJGLj78SvnLmu9zuFu2qK3IYh2exVnjV4pzMWqfjopCzDKVw79pXG8BDuvyJF e5Fg== X-Forwarded-Encrypted: i=1; AJvYcCXqTYJHhzso6Agx/ay2FFAozkjGx8oFrvt8mtJBsxXS0Lw7DCMnI4V1ARinN3QXuz4ac8U3hCJ2UcL7Dxc=@vger.kernel.org X-Gm-Message-State: AOJu0YyaHk9XRM1p2wFlZmzCXYUuM9mmk0mCNlH+xYrUEhbNI2GrR0HU iVXfu5+jmvsy0b1yOnTfOBjdFjpD4HDM4XRvKfZZ5MvTzkQQy90+wYbj3UrOqbS91R5lNKxuzST w7UkkfD0rYCFyAo6F+YQAl8koGKBmFQ== X-Received: from wmoo8-n1.prod.google.com ([2002:a05:600d:108:10b0:485:4553:1a97]) (user=sebastianene job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:4e4f:b0:485:3f72:323f with SMTP id 5b1f17b1804b1-4853f7233b2mr80282675e9.11.1773146987881; Tue, 10 Mar 2026 05:49:47 -0700 (PDT) Date: Tue, 10 Mar 2026 12:49:24 +0000 In-Reply-To: <20260310124933.830025-1-sebastianene@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260310124933.830025-1-sebastianene@google.com> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog Message-ID: <20260310124933.830025-6-sebastianene@google.com> Subject: [PATCH 05/14] irqchip/gic-v3-its: Prepare shadow structures for KVM host deprivilege From: Sebastian Ene To: alexandru.elisei@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, android-kvm@google.com Cc: catalin.marinas@arm.com, dbrazdil@google.com, joey.gouly@arm.com, kees@kernel.org, mark.rutland@arm.com, maz@kernel.org, oupton@kernel.org, perlarsen@google.com, qperret@google.com, rananta@google.com, sebastianene@google.com, smostafa@google.com, suzuki.poulose@arm.com, tabba@google.com, tglx@kernel.org, vdonnefort@google.com, bgrzesik@google.com, will@kernel.org, yuzenghui@huawei.com Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expose two helper functions to support emulated ITS in the hypervisor. These allow the KVM layer to notify the driver when hypervisor initialization is complete. The caller is expected to use the functions as follows: 1. its_start_deprivilege(): Acquire the ITS locks. 2. on_each_cpu(_kvm_host_prot_finalize, ...): Finalizes pKVM init 3. its_end_deprivilege(): Shadow the ITS structures, invoke the KVM callback, and release locks. Specifically, this shadows the ITS command queue and the 1st level indirect tables. These shadow buffers will be used by the driver after host deprivilege, while the hypervisor unmaps and takes ownership of the original structures. Signed-off-by: Sebastian Ene --- drivers/irqchip/irq-gic-v3-its.c | 165 +++++++++++++++++++++++++++-- include/linux/irqchip/arm-gic-v3.h | 24 +++++ 2 files changed, 178 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-= its.c index 291d7668cc8d..278dbc56f962 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -78,17 +78,6 @@ struct its_collection { u16 col_id; }; =20 -/* - * The ITS_BASER structure - contains memory information, cached - * value of BASER register configuration and ITS page size. - */ -struct its_baser { - void *base; - u64 val; - u32 order; - u32 psz; -}; - struct its_device; =20 /* @@ -5232,6 +5221,160 @@ static int __init its_compute_its_list_map(struct i= ts_node *its) return its_number; } =20 +static void its_free_shadow_tables(struct its_shadow_tables *shadow) +{ + int i; + + if (shadow->cmd_shadow) + its_free_pages(shadow->cmd_shadow, get_order(ITS_CMD_QUEUE_SZ)); + + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + if (!shadow->tables[i].shadow) + continue; + + its_free_pages(shadow->tables[i].shadow, 0); + } + + its_free_pages(shadow, 0); +} + +static struct its_shadow_tables *its_get_shadow_tables(struct its_node *it= s) +{ + void *page; + struct its_shadow_tables *shadow; + int i; + + page =3D its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, 0); + if (!page) + return NULL; + + shadow =3D (void *)page_address(page); + page =3D its_alloc_pages_node(its->numa_node, + GFP_KERNEL | __GFP_ZERO, + get_order(ITS_CMD_QUEUE_SZ)); + if (!page) + goto err_alloc_shadow; + + shadow->cmd_shadow =3D page_address(page); + shadow->cmdq_len =3D ITS_CMD_QUEUE_SZ; + shadow->cmd_original =3D its->cmd_base; + + memcpy(shadow->tables, its->tables, sizeof(struct its_baser) * GITS_BASER= _NR_REGS); + + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + if (!(shadow->tables[i].val & GITS_BASER_VALID)) + continue; + + if (!(shadow->tables[i].val & GITS_BASER_INDIRECT)) + continue; + + page =3D its_alloc_pages_node(its->numa_node, + GFP_KERNEL | __GFP_ZERO, + shadow->tables[i].order); + if (!page) + goto err_alloc_shadow; + + shadow->tables[i].shadow =3D page_address(page); + + memcpy(shadow->tables[i].shadow, shadow->tables[i].base, + PAGE_ORDER_TO_SIZE(shadow->tables[i].order)); + } + + return shadow; + +err_alloc_shadow: + its_free_shadow_tables(shadow); + return NULL; +} + +void *its_start_depriviledge(void) +{ + struct its_node *its; + int num_nodes =3D 0, i =3D 0; + unsigned long *flags; + + raw_spin_lock(&its_lock); + list_for_each_entry(its, &its_nodes, entry) { + num_nodes++; + } + + flags =3D kzalloc(num_nodes * sizeof(unsigned long), GFP_KERNEL_ACCOUNT); + if (!flags) { + raw_spin_unlock(&its_lock); + return NULL; + } + + list_for_each_entry(its, &its_nodes, entry) { + raw_spin_lock_irqsave(&its->lock, flags[i++]); + } + + return flags; +} +EXPORT_SYMBOL_GPL(its_start_depriviledge); + +static int its_switch_to_shadow_locked(struct its_node *its, its_init_emul= ate init_emulate_cb) +{ + struct its_shadow_tables *hyp_shadow, shadow; + int i, ret; + u64 baser, baser_phys; + + hyp_shadow =3D its_get_shadow_tables(its); + if (!hyp_shadow) + return -ENOMEM; + + memcpy(&shadow, hyp_shadow, sizeof(shadow)); + ret =3D init_emulate_cb(its->phys_base, hyp_shadow); + if (ret) { + its_free_shadow_tables(hyp_shadow); + return ret; + } + + /* Switch the driver command queue to use the shadow and save the origina= l */ + its->cmd_write =3D (its->cmd_write - its->cmd_base) + + (struct its_cmd_block *)shadow.cmd_shadow; + its->cmd_base =3D shadow.cmd_shadow; + + /* Shadow the first level of the indirect tables */ + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + baser =3D shadow.tables[i].val; + + if (!shadow.tables[i].shadow) + continue; + + baser_phys =3D virt_to_phys(shadow.tables[i].shadow); + if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) + baser_phys =3D GITS_BASER_PHYS_52_to_48(baser_phys); + + its->tables[i].val &=3D ~GENMASK(47, 12); + its->tables[i].val |=3D baser_phys; + its->tables[i].base =3D shadow.tables[i].shadow; + } + + return 0; +} + +int its_end_depriviledge(int ret_pkvm_finalize, unsigned long *flags, its_= init_emulate cb) +{ + struct its_node *its; + int i =3D 0, ret =3D 0; + + if (!flags || !cb) + return -EINVAL; + + list_for_each_entry(its, &its_nodes, entry) { + if (!ret_pkvm_finalize && !ret) + ret =3D its_switch_to_shadow_locked(its, cb); + + raw_spin_unlock_irqrestore(&its->lock, flags[i++]); + } + + kfree(flags); + raw_spin_unlock(&its_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(its_end_depriviledge); + static int __init its_probe_one(struct its_node *its) { u64 baser, tmp; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm= -gic-v3.h index 0225121f3013..40457a4375d4 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -657,6 +657,30 @@ static inline bool gic_enable_sre(void) return !!(val & ICC_SRE_EL1_SRE); } =20 +/* + * The ITS_BASER structure - contains memory information, cached + * value of BASER register configuration and ITS page size. + */ +struct its_baser { + void *base; + void *shadow; + u64 val; + u32 order; + u32 psz; +}; + +struct its_shadow_tables { + struct its_baser tables[GITS_BASER_NR_REGS]; + void *cmd_shadow; + void *cmd_original; + size_t cmdq_len; +}; + +typedef int (*its_init_emulate)(phys_addr_t its_phys_base, struct its_shad= ow_tables *shadow); + +void *its_start_depriviledge(void); +int its_end_depriviledge(int ret, unsigned long *flags, its_init_emulate c= b); + #endif =20 #endif --=20 2.53.0.473.g4a7958ca14-goog