From nobody Thu Apr 9 08:51:37 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC1FD43DA47 for ; Tue, 10 Mar 2026 09:20:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773134408; cv=none; b=KYS2zscjnNTyhQT07ig2gksXv0yy54uQzVdsQJjEsxKRF1c7JdbmE6O9boy+lcC0OBN9L7kLv8i2oFWxYWdoiLaz8D8EgMxzduttYOHg+SfRpn3lxIf6Yq77BnOhMJXEL26L+6N81jdyVOkqNOjuoYxwVcnwB6U9BGEl8ul41MQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773134408; c=relaxed/simple; bh=GSJVUxAQ4MHmSdHnYI6IronOb7V0sQaRba+BpfCLK2g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mzy2tS2yku6cP+SrHqlc+CNnLniM7+ssShcS3zRp5yWFXEJGnew8Tqvl9/LxiAQKRxIA0P7B9Ia1P0c+OTfPglAPIbDkIQYf1FMObJFhKM7pV4HUeMPwr+Wz1YYOqqDX1gtcxpG8cTo+KyU4fgncSC6j0G1szQQex2yl+GLgZww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=h6/oY3Nf; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="h6/oY3Nf" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-823c56765fdso6285722b3a.1 for ; Tue, 10 Mar 2026 02:20:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1773134405; x=1773739205; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VkopRVj6tuJbWd5GjoKb9TnBTEgj+l2ZbxAGzKv8UNM=; b=h6/oY3Nf38cK1W1GDQh1uyOe1H42OKQ5RF1f1bdFfBEuJzBNxcLSGom76KKDd/x0Y4 AqtkA5IjJaVsFqNEN86979tyoh5KEQF3775d7ryNgGNN9TcH/v/reuXz+vMxTR5BNDa3 i3tawlOwqPmWnGJ+2yKaTv5ueJavGCvdnVYlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773134405; x=1773739205; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VkopRVj6tuJbWd5GjoKb9TnBTEgj+l2ZbxAGzKv8UNM=; b=eHb3ftY/dVnK4YOKKocaNZ8BC5PPHCLAjR5PjBmH62H1+8/o/cquJyBX2Mog/xRF7c iOdYGLfU1CSmhOFbmo4Jten2tOpNnWlZOj62uFb+Dd8Smae/S83Fs5GoqHV4MIf28uo3 pdnG30HnTrYlekc+JjBLZ7ehhxhP2EfRb0QhIfqE/v7LQh9U6rAQtGdXr3KWKqiV7Hl4 Tj52y71Gry7XgoruJU1pUwlsSJkcmapcSCBWTlor6lm9d7kiJ2RBFBfTBWX1nj5vZ+B9 +/H68PW8ZqT0p3A4Fv6jhtYPFqY4TpSEPgrnUk2svPTmxu1QTmX14kLGQivF2Fvu1rao WTWA== X-Forwarded-Encrypted: i=1; AJvYcCX4d0J5I3AyD4kuxAAQ3Lqe/2a7O937T0KvLc1gT9JzKLovyaUozVd/eh2rzLFs3l0L531a3mSqpfhYonI=@vger.kernel.org X-Gm-Message-State: AOJu0YzCohVWUcPIrMfhx1nX1YvgPDidYQrvKdMlEyD8Al0lZo/dnOC0 9i9B9QJw15kOBOQxTuMf/jV3e4y0p3WQHOmJ/Cb9FQs/Ydm+ksFhC1P8KuqgmKNj5A== X-Gm-Gg: ATEYQzz+OW/52gCS2cPdA6gc0q0liq/delxqVHEEv5Z5REqxe5JsYVKSol8I5i7UWsm F91qpoqfnl/hz0Xe9sBQw5Zelv4rXvLMeOFT1auetCDn3mqi5Z1nivEETE761yBPmZHscljPViC NN0+AqJVOFPG4KncK8Cq9ioB+C6IYOROWj2zrWTglLtH8dZql/yV1qGyyL1S46kOCSPISB9BkXz AP+0El0h/Mxq9kV3+JS0S6wTwGw1op179bOW+jU+oRJKq/1OEiC1y7tld0zNvbVu8htaUSBY6Re T7Y9D48Wr/7VMXh8WWnjdJNvYtCImWnpcvjT7enxGexurNzJUhgpQJTKU2SVrNw0GY7sG1Vt4ZT 9B8BKF4uinAeWGVGlIieB+FXj1h8OO6I1gMojxKX9EwKZAa1xQydcxvRKVNakyT+KDsTg91GBKI OOhfYZLjILChU61FP2ZzgWa+ufec/Sv7i6r/pn/vpGwqu5UPEAxroJM/EwvkuzODgPJoLIzLW8r wbm5n8c X-Received: by 2002:a05:6a00:3a1c:b0:829:737e:7d77 with SMTP id d2e1a72fcca58-829a30d131dmr13244794b3a.66.1773134405103; Tue, 10 Mar 2026 02:20:05 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:ee38:e01e:e888:6900]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a48a3b74sm16965190b3a.45.2026.03.10.02.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 02:20:04 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v4 3/7] PCI: mediatek-gen3: Move controller setup steps before PERST# control Date: Tue, 10 Mar 2026 17:19:42 +0800 Message-ID: <20260310091947.2742004-4-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog In-Reply-To: <20260310091947.2742004-1-wenst@chromium.org> References: <20260310091947.2742004-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting up the translation windows and enabling MSI involve only configuring the controller, not the device. These can be done before the device is enabled. Move these steps before the existing PERST# control. This provides a cleaner separation of controller vs device setup. This also allows the later patches that split out PERST# control and add device power control to have cleaner teardown. This change only moves code. No functional change is expected. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260309215056.GA603013@bhelgaas/ Signed-off-by: Chen-Yu Tsai --- Changes since v3: - New patch --- drivers/pci/controller/pcie-mediatek-gen3.c | 50 ++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 04ae195d36c2..1b6290f2c360 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -464,6 +464,31 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) val |=3D PCIE_DISABLE_DVFSRC_VLT_REQ; writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); =20 + mtk_pcie_enable_msi(pcie); + + /* Set PCIe translation windows */ + resource_list_for_each_entry(entry, &host->windows) { + struct resource *res =3D entry->res; + unsigned long type =3D resource_type(res); + resource_size_t cpu_addr; + resource_size_t pci_addr; + resource_size_t size; + + if (type =3D=3D IORESOURCE_IO) + cpu_addr =3D pci_pio_to_address(res->start); + else if (type =3D=3D IORESOURCE_MEM) + cpu_addr =3D res->start; + else + continue; + + pci_addr =3D res->start - entry->offset; + size =3D resource_size(res); + err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, + type, &table_index); + if (err) + return err; + } + /* * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal * causing occasional PCIe link down. In order to overcome the issue, @@ -510,31 +535,6 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) return err; } =20 - mtk_pcie_enable_msi(pcie); - - /* Set PCIe translation windows */ - resource_list_for_each_entry(entry, &host->windows) { - struct resource *res =3D entry->res; - unsigned long type =3D resource_type(res); - resource_size_t cpu_addr; - resource_size_t pci_addr; - resource_size_t size; - - if (type =3D=3D IORESOURCE_IO) - cpu_addr =3D pci_pio_to_address(res->start); - else if (type =3D=3D IORESOURCE_MEM) - cpu_addr =3D res->start; - else - continue; - - pci_addr =3D res->start - entry->offset; - size =3D resource_size(res); - err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, - type, &table_index); - if (err) - return err; - } - return 0; } =20 --=20 2.53.0.473.g4a7958ca14-goog