From nobody Thu Apr 9 08:55:24 2026 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83C79364EAE for ; Tue, 10 Mar 2026 07:56:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773129380; cv=none; b=QqMOqv3pJ3BNzk6mTqzKnf0h50dQnBu9fGIsJZawMajl11N+rYMt91eVt+sViJXo4xtlpxV+6OJIgAfBQUeZ8Swkmum+t9NppC3nW6Eb1V1//2619Fk4s6FE4Ix+dsok9EymfY4ehJiAwlCBIxix2bBGYqlprAPzrrWxrfXZNq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773129380; c=relaxed/simple; bh=pGcfVVvTw1ZWJSV+BA7Cqfi35R8O7VoHAutQcsJ0fqw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Eski8Cvc+aipKzSCUAsMB57OEEJ3DOrod+/bNSc75jxdQmxpicriPofeFLKo9s/CihE7ZpDAGPfqyyOIKk77KkxdDiQse9NKhMTE2PzyErlwkwyA0IUNXjd+KffhfmLuJXLkWhf+GG6nBigu3e4oJFhmRv6s+yNTQ2Cjnb320Kg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=YNC9YuDH; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="YNC9YuDH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; s=k1; bh=7vMrLv9qF9Z71L0B1gC3rLo8m3rNp4D4vQ0xv92urq4=; b=YNC9Yu DHC3vdwaWt2Df0cLQz6Ae1g+4lNqNEgGP1+fNns87u8cQatlnO1vaa0Mes8ZFQH7 PJAXsFjtx4+TrgxY4ZbzG1bP6aXInekXTMPeaGSU1zHEO1NPpj2iBt2nhEmU7WqE hTaNU1sA6tgyZnZpVVtIKDGHSDk3I/t8h14iqr4+bIezwHrQgg8UZOlfy48+bCKt 9tVD0f1TGWr07nvUoX9gM78YMNN0ykgiCZxT345ErLlw/0ZiAjPuBgb1ZDDUstE0 k27fSpeE7vuCsb+bE+Q0OKi/o0tq9gy660pnQVlMaM1a92g4v6p+i1TNR6vZJdad zNMR4SULu68i5DWA== Received: (qmail 3112682 invoked from network); 10 Mar 2026 08:55:53 +0100 Received: by mail.zeus03.de with UTF8SMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Mar 2026 08:55:53 +0100 X-UD-Smtp-Session: l3s3148p1@3Qs92aZMxpAujntP From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Wolfram Sang , Konrad Dybcio , Bjorn Andersson , Baolin Wang , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v4 06/15] hwspinlock: qcom: use new callback to initialize hwspinlock priv Date: Tue, 10 Mar 2026 08:55:21 +0100 Message-ID: <20260310075539.11701-7-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260310075539.11701-1-wsa+renesas@sang-engineering.com> References: <20260310075539.11701-1-wsa+renesas@sang-engineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Apply the new helper to avoid using internal structures from the core. Remove superfluous setting of drvdata while here. Signed-off-by: Wolfram Sang Acked-by: Konrad Dybcio --- drivers/hwspinlock/qcom_hwspinlock.c | 45 ++++++++++++++++------------ 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom= _hwspinlock.c index 7960a4972eab..73b280988109 100644 --- a/drivers/hwspinlock/qcom_hwspinlock.c +++ b/drivers/hwspinlock/qcom_hwspinlock.c @@ -25,6 +25,13 @@ struct qcom_hwspinlock_of_data { const struct regmap_config *regmap_config; }; =20 +struct qcom_hwspinlock_priv_init_data { + struct device *dev; + struct regmap *regmap; + u32 base; + u32 stride; +}; + static int qcom_hwspinlock_trylock(struct hwspinlock *lock) { struct regmap_field *field =3D hwspin_lock_get_priv(lock); @@ -89,10 +96,23 @@ static int qcom_hwspinlock_bust(struct hwspinlock *lock= , unsigned int id) return 0; } =20 +static void *qcom_hwspinlock_init_priv(int local_id, void *init_data) +{ + struct qcom_hwspinlock_priv_init_data *init =3D init_data; + struct reg_field field; + + field.reg =3D init->base + local_id * init->stride; + field.lsb =3D 0; + field.msb =3D 31; + + return devm_regmap_field_alloc(init->dev, init->regmap, field); +} + static const struct hwspinlock_ops qcom_hwspinlock_ops =3D { .trylock =3D qcom_hwspinlock_trylock, .unlock =3D qcom_hwspinlock_unlock, .bust =3D qcom_hwspinlock_bust, + .init_priv =3D qcom_hwspinlock_init_priv, }; =20 static const struct regmap_config sfpb_mutex_config =3D { @@ -202,17 +222,14 @@ static struct regmap *qcom_hwspinlock_probe_mmio(stru= ct platform_device *pdev, =20 static int qcom_hwspinlock_probe(struct platform_device *pdev) { + struct qcom_hwspinlock_priv_init_data init; struct hwspinlock_device *bank; - struct reg_field field; struct regmap *regmap; size_t array_size; - u32 stride; - u32 base; - int i; =20 - regmap =3D qcom_hwspinlock_probe_syscon(pdev, &base, &stride); + regmap =3D qcom_hwspinlock_probe_syscon(pdev, &init.base, &init.stride); if (IS_ERR(regmap) && PTR_ERR(regmap) =3D=3D -ENODEV) - regmap =3D qcom_hwspinlock_probe_mmio(pdev, &base, &stride); + regmap =3D qcom_hwspinlock_probe_mmio(pdev, &init.base, &init.stride); =20 if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -222,21 +239,11 @@ static int qcom_hwspinlock_probe(struct platform_devi= ce *pdev) if (!bank) return -ENOMEM; =20 - platform_set_drvdata(pdev, bank); - - for (i =3D 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { - field.reg =3D base + i * stride; - field.lsb =3D 0; - field.msb =3D 31; - - bank->lock[i].priv =3D devm_regmap_field_alloc(&pdev->dev, - regmap, field); - if (IS_ERR(bank->lock[i].priv)) - return PTR_ERR(bank->lock[i].priv); - } + init.dev =3D &pdev->dev; + init.regmap =3D regmap; =20 return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops, - 0, QCOM_MUTEX_NUM_LOCKS, NULL); + 0, QCOM_MUTEX_NUM_LOCKS, &init); } =20 static struct platform_driver qcom_hwspinlock_driver =3D { --=20 2.47.3