From nobody Wed Apr 8 19:15:28 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C51C3B95E3 for ; Tue, 10 Mar 2026 03:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773114002; cv=none; b=OoL/+kVgXZiiwF4YU64Qhb8Dl++vR++s6dCg49weuJLEVY5TlPpUJup8Jw/nEom/B7extNKQIyUg5/8ARgEoqvA+vkn75K+HdVboaa+DZ64v2TUfk/QwOiXuvoksui1ujlfTMsz+6/gwmmfCbPO/G2r0vPYM3zktVg6Yg/8xpbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773114002; c=relaxed/simple; bh=NdHOhxDB5X511h77TiK0y3+SbRf+3iHy43ELTPyc6yU=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=gWbIhdO1rw0hIhElICtUz2zZnf8tKr6GjeDXgpKS06PCNuxgrrYYjWjzV/rrKmncajaDaFbQx2Tpf466mVkrjqWx4/KG2aFjkxJpb3iz2zeYnRbwXlFgZTp20r9+5oP/4IOe5935mL3pC6cgTDIHmsQ15rXnTXRjLiBHBKpN1X0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=dn3elXuS; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="dn3elXuS" X-UUID: c96877c41c3211f1a39cd589f645bc18-20260310 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=6KEPQoelIaSRZixu2FcCj8GjygNUojPP6SBnzoaIaQY=; b=dn3elXuSOMc/ZhVpFeTpGSkt5AawsCldeNzBhrwCLr0m4xlPcMAC4sSl8aTzG+uZuOQTPO1UBnqG1zNlO+12W1MYUvHXHLqPe9mywZw0DRdlimrIzm/+jl91jiwwnmnGlQpoVcRN9lR7VsHTQrodeEWugHhWokExR9OTNOvAD6Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:8c98addf-0fb4-48f2-8dfe-9d6874d91289,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:89c9d04,CLOUDID:7c2f71ea-ef90-4382-9c6f-55f2a0689a6b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102|836|888|898,TC:-5,Content:0|15|5 0,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI:0,OSA :0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: c96877c41c3211f1a39cd589f645bc18-20260310 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1932731618; Tue, 10 Mar 2026 11:39:47 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 10 Mar 2026 11:39:46 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 10 Mar 2026 11:39:45 +0800 From: Zexin Wang To: Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Zexin Wang , Sirius Wang , "Jack Hsu" , Vince Liu Subject: [PATCH] reset-controller: ti: introduce a new reset handler Date: Tue, 10 Mar 2026 11:39:35 +0800 Message-ID: <20260310033942.29585-1-ot_zexin.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce ti_syscon_reset() to integrate assert and deassert together. If some modules need do serialized assert and deassert operations to reset itself, reset_control_reset can be called for convenience. Signed-off-by: Zexin Wang --- drivers/reset/reset-ti-syscon.c | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-sysco= n.c index 23f86ddb8668..f37685e32b0a 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -7,6 +7,7 @@ * Suman Anna */ =20 +#include #include #include #include @@ -42,12 +43,14 @@ struct ti_syscon_reset_control { * @regmap: regmap handle containing the memory-mapped reset registers * @controls: array of reset controls * @nr_controls: number of controls in control array + * @reset_duration_us: time of controller assert reset */ struct ti_syscon_reset_data { struct reset_controller_dev rcdev; struct regmap *regmap; struct ti_syscon_reset_control *controls; unsigned int nr_controls; + unsigned int reset_duration_us; }; =20 #define to_ti_syscon_reset_data(_rcdev) \ @@ -150,9 +153,37 @@ static int ti_syscon_reset_status(struct reset_control= ler_dev *rcdev, !(control->flags & STATUS_SET); } =20 +/** + * ti_syscon_reset() - perform a full reset cycle on a device + * @rcdev: reset controller entity + * @id: ID of the reset to be asserted and deasserted + * + * This function performs a full reset cycle by asserting and then + * deasserting the reset signal for a device. It ensures the device + * is properly reset and ready for operation. + * + * Return: 0 for successful request, else a corresponding error value + */ +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_syscon_reset_data *data =3D to_ti_syscon_reset_data(rcdev); + int ret; + + ret =3D ti_syscon_reset_assert(rcdev, id); + if (ret) + return ret; + + if (data->reset_duration_us) + usleep_range(data->reset_duration_us, data->reset_duration_us * 2); + + return ti_syscon_reset_deassert(rcdev, id); +} + static const struct reset_control_ops ti_syscon_reset_ops =3D { .assert =3D ti_syscon_reset_assert, .deassert =3D ti_syscon_reset_deassert, + .reset =3D ti_syscon_reset, .status =3D ti_syscon_reset_status, }; =20 @@ -196,6 +227,9 @@ static int ti_syscon_reset_probe(struct platform_device= *pdev) controls[i].flags =3D be32_to_cpup(list++); } =20 + of_property_read_u32(pdev->dev.of_node, "reset-duration-us", + &data->reset_duration_us); + data->rcdev.ops =3D &ti_syscon_reset_ops; data->rcdev.owner =3D THIS_MODULE; data->rcdev.of_node =3D np; --=20 2.45.2