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charset="utf-8" Add dedicated FB HALs for Hopper (GH100) and Blackwell (GB100) with architecture-specific non-WPR heap sizes. Hopper uses 2 MiB, Blackwell uses 2 MiB + 128 KiB. These are needed for the larger reserved memory regions that Hopper/Blackwell GPUs require. Also adds the non_wpr_heap_size() method to the FbHal trait, and the total_reserved_size field to FbLayout. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 16 ++++++++--- drivers/gpu/nova-core/fb/hal.rs | 16 ++++++++--- drivers/gpu/nova-core/fb/hal/ga102.rs | 2 +- drivers/gpu/nova-core/fb/hal/gb100.rs | 38 +++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/gh100.rs | 38 +++++++++++++++++++++++++++ 5 files changed, 102 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/nova-core/fb/hal/gb100.rs create mode 100644 drivers/gpu/nova-core/fb/hal/gh100.rs diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index ffb996b918f8..c12705f5f742 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -31,7 +31,7 @@ regs, }; =20 -mod hal; +pub(crate) mod hal; =20 /// Type holding the sysmem flush memory page, a page of memory to be writ= ten into the /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory= coherency. @@ -99,6 +99,15 @@ pub(crate) fn unregister(&self, bar: &Bar0) { } } =20 +/// Calculate non-WPR heap size based on chipset architecture. +/// This matches the logic used in FSP for consistency. +pub(crate) fn calc_non_wpr_heap_size(chipset: Chipset) -> u64 { + hal::fb_hal(chipset) + .non_wpr_heap_size() + .map(u64::from) + .unwrap_or(usize_as_u64(SZ_1M)) +} + pub(crate) struct FbRange(Range); =20 impl FbRange { @@ -253,9 +262,8 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw:= &GspFirmware) -> Result< }; =20 let heap =3D { - const HEAP_SIZE: u64 =3D usize_as_u64(SZ_1M); - - FbRange(wpr2.start - HEAP_SIZE..wpr2.start) + let heap_size =3D calc_non_wpr_heap_size(chipset); + FbRange(wpr2.start - heap_size..wpr2.start) }; =20 Ok(Self { diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index d33ca0f96417..ebd12247f771 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -12,6 +12,8 @@ =20 mod ga100; mod ga102; +mod gb100; +mod gh100; mod tu102; =20 pub(crate) trait FbHal { @@ -28,14 +30,22 @@ pub(crate) trait FbHal { =20 /// Returns the VRAM size, in bytes. fn vidmem_size(&self, bar: &Bar0) -> u64; + + /// Returns the non-WPR heap size for GPUs that need large reserved me= mory. + /// + /// Returns `None` for GPUs that don't need extra reserved memory. + fn non_wpr_heap_size(&self) -> Option { + None + } } =20 /// Returns the HAL corresponding to `chipset`. -pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { +pub(crate) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { match chipset.arch() { Architecture::Turing =3D> tu102::TU102_HAL, Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> ga100::= GA100_HAL, - Architecture::Ampere =3D> ga102::GA102_HAL, - Architecture::Ada | Architecture::Hopper | Architecture::Blackwell= =3D> ga102::GA102_HAL, + Architecture::Ampere | Architecture::Ada =3D> ga102::GA102_HAL, + Architecture::Hopper =3D> gh100::GH100_HAL, + Architecture::Blackwell =3D> gb100::GB100_HAL, } } diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index 734605905031..f8d8f01e3c5d 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -8,7 +8,7 @@ regs, // }; =20 -fn vidmem_size_ga102(bar: &Bar0) -> u64 { +pub(super) fn vidmem_size_ga102(bar: &Bar0) -> u64 { regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size() } =20 diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs new file mode 100644 index 000000000000..bead99a6ca76 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gb100; + +impl FbHal for Gb100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn non_wpr_heap_size(&self) -> Option { + // 2 MiB + 128 KiB non-WPR heap for Blackwell (see Open RM: kgspCa= lculateFbLayout_GB100). + Some(0x220000) + } +} + +const GB100: Gb100 =3D Gb100; +pub(super) const GB100_HAL: &dyn FbHal =3D &GB100; diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/= fb/hal/gh100.rs new file mode 100644 index 000000000000..32d7414e6243 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gh100; + +impl FbHal for Gh100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn non_wpr_heap_size(&self) -> Option { + // 2 MiB non-WPR heap for Hopper (see Open RM: kgspCalculateFbLayo= ut_GH100). + Some(0x200000) + } +} + +const GH100: Gh100 =3D Gh100; +pub(super) const GH100_HAL: &dyn FbHal =3D &GH100; --=20 2.53.0