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Tue, 10 Mar 2026 11:41:41 +0000 (GMT) Received: from NP-A-BELLE.kl.imgtec.org (172.25.8.171) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Tue, 10 Mar 2026 11:41:40 +0000 From: Alessio Belle Date: Tue, 10 Mar 2026 11:41:12 +0000 Subject: [PATCH 2/2] drm/imagination: Disable interrupts before suspending the GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260310-drain-irqs-before-suspend-v1-2-bf4f9ed68e75@imgtec.com> References: <20260310-drain-irqs-before-suspend-v1-0-bf4f9ed68e75@imgtec.com> In-Reply-To: <20260310-drain-irqs-before-suspend-v1-0-bf4f9ed68e75@imgtec.com> To: Frank Binns , Matt Coster , Brajesh Gupta , "Alexandru Dadu" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Alessio Belle" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773142899; l=2905; i=alessio.belle@imgtec.com; s=20251208; h=from:subject:message-id; bh=rfcImWO5u1M6GgdhPBmqgLwi5anOe3Jmg2zQkfeUrAo=; b=fqUMI3DCl0PpmNyhvy6RnD5uGu6Dng/YeRjwvR0koR0bhOARrFPJW0Y20+uLDS0itlh12IhEI fyNPDsRv/lnBqMqadIgG4Y36+2d9eB1Erm79ks3iVivqfMUgDjeXbAk X-Developer-Key: i=alessio.belle@imgtec.com; a=ed25519; pk=2Vtuk+GKBRjwMqIHpKk+Gx6zl7cgtq0joszcOc0zF4g= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDEwMSBTYWx0ZWRfX6H5PP5MKUvr6 IvqmV00Ba1o0rqWw7d5/bdYuiijgkSrycavmtgWm1+6wGzQUjSIE3NO1GXZvH7Pc2FWsbhVMpLE +ytyr9kTmOib5bwLIxb7hf0uFNovruwcJ2IcabR0ypQ+jYxCKj03YHWhtcffi+q8DlnEFL2I58s pEUPJP53cUWV+rlkkOBFWIFWGoIq8bV/Nz2reg5KYoaHZAmaH5PQfD5fnE2cY4BNX2C3sjBziDy U0zKGDJCkhC1pEQrV90qa6JxaquK10TNZ26ZUNdZbaZ7l0fjBqRWPolreB65JolUcFfpyXI3AnV BC0OHhlBc3viMBrxrNi92sTedhj4Rvr6ICen9VqYcWy73N0/eJ/kZnuFSd0VV95p7evSlyCQDvd bVsoeUjWZbo2kYGFwv9AorMkyLj6Tut6DElQhGBu7lwrvaP2bt8DXxbVvqoAYLN397nkOX78d0/ L48IFvV1K33/wUvk/iQ== X-Proofpoint-GUID: f6cPMCgM9sI0iDjosLxUyRTo7wqXtXbM X-Proofpoint-ORIG-GUID: f6cPMCgM9sI0iDjosLxUyRTo7wqXtXbM X-Authority-Analysis: v=2.4 cv=MuhfKmae c=1 sm=1 tr=0 ts=69b00375 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=Rd4DrVCMV_EA:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=kQ-hrUj2-E3RCbRHssb7:22 a=7RYWX5rxfSByPNLylY2M:22 a=r_1tXGB3AAAA:8 a=qGs6vJjZfZ_MceZGOfAA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 This is an additional safety layer to ensure no accesses to the GPU registers can be made while it is powered off. While we can disable IRQ generation from GPU, META firmware, MIPS firmware and for safety events, we cannot do the same for the RISC-V firmware. To keep a unified approach, once the firmware has completed its power off sequence, disable IRQs for the while GPU at the kernel level instead. Signed-off-by: Alessio Belle --- drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++++++++------= ---- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index f50cdea30680..3f22b07e3301 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -92,9 +92,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) static int pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm= _suspend) { - if (!hard_reset) { - int err; + int err; =20 + if (!hard_reset) { cancel_delayed_work_sync(&pvr_dev->watchdog.work); =20 err =3D pvr_power_request_idle(pvr_dev); @@ -107,33 +107,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool= hard_reset, bool rpm_suspe } =20 if (rpm_suspend) { - /* Wait for late processing of GPU or firmware IRQs in other cores */ - synchronize_irq(pvr_dev->irq); + /* This also waits for late processing of GPU or firmware IRQs in other = cores */ + disable_irq(pvr_dev->irq); } =20 - return pvr_fw_stop(pvr_dev); + err =3D pvr_fw_stop(pvr_dev); + if (err && rpm_suspend) + enable_irq(pvr_dev->irq); + + return err; } =20 static int -pvr_power_fw_enable(struct pvr_device *pvr_dev) +pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) { int err; =20 + if (rpm_resume) + enable_irq(pvr_dev->irq); + err =3D pvr_fw_start(pvr_dev); if (err) - return err; + goto out; =20 err =3D pvr_wait_for_fw_boot(pvr_dev); if (err) { drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); pvr_fw_stop(pvr_dev); - return err; + goto out; } =20 queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, msecs_to_jiffies(WATCHDOG_TIME_MS)); =20 return 0; + +out: + if (rpm_resume) + disable_irq(pvr_dev->irq); + + return err; } =20 bool @@ -396,7 +409,7 @@ pvr_power_device_resume(struct device *dev) goto err_drm_dev_exit; =20 if (pvr_dev->fw_dev.booted) { - err =3D pvr_power_fw_enable(pvr_dev); + err =3D pvr_power_fw_enable(pvr_dev, true); if (err) goto err_power_off; } @@ -546,7 +559,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_r= eset) =20 pvr_fw_irq_clear(pvr_dev); =20 - err =3D pvr_power_fw_enable(pvr_dev); + err =3D pvr_power_fw_enable(pvr_dev, false); } =20 if (err && hard_reset) --=20 2.43.0