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Tue, 10 Mar 2026 11:41:40 +0000 (GMT) Received: from NP-A-BELLE.kl.imgtec.org (172.25.8.171) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Tue, 10 Mar 2026 11:41:39 +0000 From: Alessio Belle Date: Tue, 10 Mar 2026 11:41:11 +0000 Subject: [PATCH 1/2] drm/imagination: Synchronize interrupts before suspending the GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260310-drain-irqs-before-suspend-v1-1-bf4f9ed68e75@imgtec.com> References: <20260310-drain-irqs-before-suspend-v1-0-bf4f9ed68e75@imgtec.com> In-Reply-To: <20260310-drain-irqs-before-suspend-v1-0-bf4f9ed68e75@imgtec.com> To: Frank Binns , Matt Coster , Brajesh Gupta , "Alexandru Dadu" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Alessio Belle" , X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Depending on timing, the IRQ handler could be running while the GPU is suspended, leading to kernel crashes when trying to access GPU registers. See example signature below. In a power off sequence initiated by the runtime PM suspend callback, wait for any IRQ handlers in progress on other CPU cores to finish, by calling synchronize_irq(). At the same time, remove the runtime PM resume/put calls in the threaded IRQ handler. On top of not being the right approach to begin with, and being at the wrong place as they should have wrapped all GPU register accesses, the driver would hit a deadlock between synchronize_irq() being called from a runtime PM suspend callback, holding the device power lock, and the resume callback requiring the same. Example crash signature on a TI AM68 SK platform: [ 337.241218] SError Interrupt on CPU0, code 0x00000000bf000000 -- SError [ 337.241239] CPU: 0 UID: 0 PID: 112 Comm: irq/234-gpu Tainted: G M = 6.17.7-B2C-00005-g9c7bbe4ea16c #2 PREEMPT [ 337.241246] Tainted: [M]=3DMACHINE_CHECK [ 337.241249] Hardware name: Texas Instruments AM68 SK (DT) [ 337.241252] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYP= E=3D--) [ 337.241256] pc : pvr_riscv_irq_pending+0xc/0x24 [ 337.241277] lr : pvr_device_irq_thread_handler+0x64/0x310 [ 337.241282] sp : ffff800085b0bd30 [ 337.241284] x29: ffff800085b0bd50 x28: ffff0008070d9eab x27: ffff80008= 3a5ce10 [ 337.241291] x26: ffff000806e48f80 x25: ffff0008070d9eac x24: 000000000= 0000000 [ 337.241296] x23: ffff0008068e9bf0 x22: ffff0008068e9bd0 x21: ffff80008= 5b0bd30 [ 337.241301] x20: ffff0008070d9e00 x19: ffff0008068e9000 x18: 000000000= 0000001 [ 337.241305] x17: 637365645f656c70 x16: 0000000000000000 x15: ffff000b7= df9ff40 [ 337.241310] x14: 0000a585fe3c0d0e x13: 000000999704f060 x12: 000000000= 002771a [ 337.241314] x11: 00000000000000c0 x10: 0000000000000af0 x9 : ffff80008= 5b0bd00 [ 337.241318] x8 : ffff0008071175d0 x7 : 000000000000b955 x6 : 000000000= 0000003 [ 337.241323] x5 : 0000000000000000 x4 : 0000000000000002 x3 : 000000000= 0000000 [ 337.241327] x2 : ffff800080e39d20 x1 : ffff800080e3fc48 x0 : 000000000= 0000000 [ 337.241333] Kernel panic - not syncing: Asynchronous SError Interrupt [ 337.241337] CPU: 0 UID: 0 PID: 112 Comm: irq/234-gpu Tainted: G M = 6.17.7-B2C-00005-g9c7bbe4ea16c #2 PREEMPT [ 337.241342] Tainted: [M]=3DMACHINE_CHECK [ 337.241343] Hardware name: Texas Instruments AM68 SK (DT) [ 337.241345] Call trace: [ 337.241348] show_stack+0x18/0x24 (C) [ 337.241357] dump_stack_lvl+0x60/0x80 [ 337.241364] dump_stack+0x18/0x24 [ 337.241368] vpanic+0x124/0x2ec [ 337.241373] abort+0x0/0x4 [ 337.241377] add_taint+0x0/0xbc [ 337.241384] arm64_serror_panic+0x70/0x80 [ 337.241389] do_serror+0x3c/0x74 [ 337.241392] el1h_64_error_handler+0x30/0x48 [ 337.241400] el1h_64_error+0x6c/0x70 [ 337.241404] pvr_riscv_irq_pending+0xc/0x24 (P) [ 337.241410] irq_thread_fn+0x2c/0xb0 [ 337.241416] irq_thread+0x170/0x334 [ 337.241421] kthread+0x12c/0x210 [ 337.241428] ret_from_fork+0x10/0x20 [ 337.241434] SMP: stopping secondary CPUs [ 337.241451] Kernel Offset: disabled [ 337.241453] CPU features: 0x040000,02002800,20002001,0400421b [ 337.241456] Memory Limit: none [ 337.457921] ---[ end Kernel panic - not syncing: Asynchronous SError I= nterrupt ]--- Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure an= d META FW support") Fixes: 96822d38ff57 ("drm/imagination: Handle Rogue safety event IRQs") Cc: # see patch description, needs adjustments for= < 6.16 Signed-off-by: Alessio Belle Reviewed-by: Matt Coster --- 96822d38ff57 only appeared in 6.16, so the change in pvr_device.c isn't needed before that, but the rest of the fix is applicable to earlier stable branches which contain cc1aeedb98ad. --- drivers/gpu/drm/imagination/pvr_device.c | 17 ----------------- drivers/gpu/drm/imagination/pvr_power.c | 11 ++++++++--- 2 files changed, 8 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index f58bb66a6327..dbb6f5a8ded1 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -225,29 +225,12 @@ static irqreturn_t pvr_device_irq_thread_handler(int = irq, void *data) } =20 if (pvr_dev->has_safety_events) { - int err; - - /* - * Ensure the GPU is powered on since some safety events (such - * as ECC faults) can happen outside of job submissions, which - * are otherwise the only time a power reference is held. - */ - err =3D pvr_power_get(pvr_dev); - if (err) { - drm_err_ratelimited(drm_dev, - "%s: could not take power reference (%d)\n", - __func__, err); - return ret; - } - while (pvr_device_safety_irq_pending(pvr_dev)) { pvr_device_safety_irq_clear(pvr_dev); pvr_device_handle_safety_events(pvr_dev); =20 ret =3D IRQ_HANDLED; } - - pvr_power_put(pvr_dev); } =20 return ret; diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index 7a8765c0c1ed..f50cdea30680 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -90,7 +90,7 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) } =20 static int -pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset) +pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm= _suspend) { if (!hard_reset) { int err; @@ -106,6 +106,11 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool = hard_reset) return err; } =20 + if (rpm_suspend) { + /* Wait for late processing of GPU or firmware IRQs in other cores */ + synchronize_irq(pvr_dev->irq); + } + return pvr_fw_stop(pvr_dev); } =20 @@ -361,7 +366,7 @@ pvr_power_device_suspend(struct device *dev) return -EIO; =20 if (pvr_dev->fw_dev.booted) { - err =3D pvr_power_fw_disable(pvr_dev, false); + err =3D pvr_power_fw_disable(pvr_dev, false, true); if (err) goto err_drm_dev_exit; } @@ -518,7 +523,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_r= eset) queues_disabled =3D true; } =20 - err =3D pvr_power_fw_disable(pvr_dev, hard_reset); + err =3D pvr_power_fw_disable(pvr_dev, hard_reset, false); if (!err) { if (hard_reset) { pvr_dev->fw_dev.booted =3D false; --=20 2.43.0 From nobody Thu Apr 9 06:37:28 2026 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F731388E65 for ; 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a=ed25519-sha256; t=1773142899; l=2905; i=alessio.belle@imgtec.com; s=20251208; h=from:subject:message-id; bh=rfcImWO5u1M6GgdhPBmqgLwi5anOe3Jmg2zQkfeUrAo=; b=fqUMI3DCl0PpmNyhvy6RnD5uGu6Dng/YeRjwvR0koR0bhOARrFPJW0Y20+uLDS0itlh12IhEI fyNPDsRv/lnBqMqadIgG4Y36+2d9eB1Erm79ks3iVivqfMUgDjeXbAk X-Developer-Key: i=alessio.belle@imgtec.com; a=ed25519; pk=2Vtuk+GKBRjwMqIHpKk+Gx6zl7cgtq0joszcOc0zF4g= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDEwMSBTYWx0ZWRfX6H5PP5MKUvr6 IvqmV00Ba1o0rqWw7d5/bdYuiijgkSrycavmtgWm1+6wGzQUjSIE3NO1GXZvH7Pc2FWsbhVMpLE +ytyr9kTmOib5bwLIxb7hf0uFNovruwcJ2IcabR0ypQ+jYxCKj03YHWhtcffi+q8DlnEFL2I58s pEUPJP53cUWV+rlkkOBFWIFWGoIq8bV/Nz2reg5KYoaHZAmaH5PQfD5fnE2cY4BNX2C3sjBziDy U0zKGDJCkhC1pEQrV90qa6JxaquK10TNZ26ZUNdZbaZ7l0fjBqRWPolreB65JolUcFfpyXI3AnV BC0OHhlBc3viMBrxrNi92sTedhj4Rvr6ICen9VqYcWy73N0/eJ/kZnuFSd0VV95p7evSlyCQDvd bVsoeUjWZbo2kYGFwv9AorMkyLj6Tut6DElQhGBu7lwrvaP2bt8DXxbVvqoAYLN397nkOX78d0/ L48IFvV1K33/wUvk/iQ== X-Proofpoint-GUID: f6cPMCgM9sI0iDjosLxUyRTo7wqXtXbM X-Proofpoint-ORIG-GUID: f6cPMCgM9sI0iDjosLxUyRTo7wqXtXbM X-Authority-Analysis: v=2.4 cv=MuhfKmae c=1 sm=1 tr=0 ts=69b00375 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=Rd4DrVCMV_EA:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=kQ-hrUj2-E3RCbRHssb7:22 a=7RYWX5rxfSByPNLylY2M:22 a=r_1tXGB3AAAA:8 a=qGs6vJjZfZ_MceZGOfAA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 This is an additional safety layer to ensure no accesses to the GPU registers can be made while it is powered off. While we can disable IRQ generation from GPU, META firmware, MIPS firmware and for safety events, we cannot do the same for the RISC-V firmware. To keep a unified approach, once the firmware has completed its power off sequence, disable IRQs for the while GPU at the kernel level instead. Signed-off-by: Alessio Belle Reviewed-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++++++++------= ---- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index f50cdea30680..3f22b07e3301 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -92,9 +92,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) static int pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm= _suspend) { - if (!hard_reset) { - int err; + int err; =20 + if (!hard_reset) { cancel_delayed_work_sync(&pvr_dev->watchdog.work); =20 err =3D pvr_power_request_idle(pvr_dev); @@ -107,33 +107,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool= hard_reset, bool rpm_suspe } =20 if (rpm_suspend) { - /* Wait for late processing of GPU or firmware IRQs in other cores */ - synchronize_irq(pvr_dev->irq); + /* This also waits for late processing of GPU or firmware IRQs in other = cores */ + disable_irq(pvr_dev->irq); } =20 - return pvr_fw_stop(pvr_dev); + err =3D pvr_fw_stop(pvr_dev); + if (err && rpm_suspend) + enable_irq(pvr_dev->irq); + + return err; } =20 static int -pvr_power_fw_enable(struct pvr_device *pvr_dev) +pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) { int err; =20 + if (rpm_resume) + enable_irq(pvr_dev->irq); + err =3D pvr_fw_start(pvr_dev); if (err) - return err; + goto out; =20 err =3D pvr_wait_for_fw_boot(pvr_dev); if (err) { drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); pvr_fw_stop(pvr_dev); - return err; + goto out; } =20 queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, msecs_to_jiffies(WATCHDOG_TIME_MS)); =20 return 0; + +out: + if (rpm_resume) + disable_irq(pvr_dev->irq); + + return err; } =20 bool @@ -396,7 +409,7 @@ pvr_power_device_resume(struct device *dev) goto err_drm_dev_exit; =20 if (pvr_dev->fw_dev.booted) { - err =3D pvr_power_fw_enable(pvr_dev); + err =3D pvr_power_fw_enable(pvr_dev, true); if (err) goto err_power_off; } @@ -546,7 +559,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_r= eset) =20 pvr_fw_irq_clear(pvr_dev); =20 - err =3D pvr_power_fw_enable(pvr_dev); + err =3D pvr_power_fw_enable(pvr_dev, false); } =20 if (err && hard_reset) --=20 2.43.0